Cypress CY7C1443AV33, CY7C1441AV33, CY7C1447AV33 manual ZZ Mode Timing28

Page 25

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Timing Diagrams (continued)

Figure 6. ZZ Mode Timing[28, 29]

CLK

t ZZ

t ZZI

ISUPPLY

I DDZZ

ALL INPUTS (except ZZ)

t ZZREC

t RZZI

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Note

28.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

29.DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05357 Rev. *G

Page 25 of 31

[+] Feedback

Image 25

Contents Selection Guide Functional Description FeaturesDescription 133 MHz 100 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1443AV33 2Mx Logic Block Diagram CY7C1441AV33 1M xBWE Enable CE1 Register CE2 CE3 Logic Block Diagram CY7C1447AV33 512K xCY7C1441AV33 Pin ConfigurationsCY7C1443AV33 2M x BWE Adsc ADV TDI TDO ModeAdsp DQP CDQ G DQ G DQ BDQ B DQP G DQP C DQP DQ CName Description Pin DefinitionsByte Write Select Inputs, Active LOW. Qualified with Power Supply for the IO Circuitry Power Supply Inputs to the Core of the DeviceGround for the Core of the Device Ground for the IO CircuitryFunctional Overview Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Truth Table ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Cycle DescriptionTruth Table for Read/Write Partial Truth Table for Read/WriteFunction CY7C1441AV33 2 Function CY7C1443AV33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramInstruction Register TAP Instruction SetExtest TAP TimingSetup Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Hold Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Conditions Min Max UnitScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeCY7C1441AV33 1M x 36, CY7C1443AV33 2M x Bit # Ball ID Ball Fbga Boundary Scan Order13,14Bit # Ball ID DC Electrical Characteristics Over the Operating Range Electrical Characteristics Over the Operating Range15Maximum Ratings Operating RangeThermal Resistance Capacitance100 Unit Parameter Min Max Switching CharacteristicsOutput Times Adsp Adsc Timing DiagramsData Out Q High-Z QA1 ADV suspends burstWrite Cycle Timing24 Read/Write Cycle Timing24, 26 ZZ Mode Timing28 Ordering Information Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x1.76 mm CJM Issue Date Orig. Description of ChangeSYT VKN RXUVKN/AESA