Cypress CY7C1447AV33, CY7C1441AV33, CY7C1443AV33 manual TAP Timing, Extest

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

EXTEST

The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the shift-DR controller state.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #89 (for 165-FBGA package) or bit #138 (for 209-FBGA package). When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current

instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

1

2

Test Clock

 

(TCK)

tTH

 

tTMSS

tTMSH

Test Mode Select (TMS)

tTDIS tTDIH

Test Data-In (TDI)

3

4

5

6

tTL

tCYC

 

 

tTDOV

tTDOX

Test Data-Out (TDO)

DON’T CARE

UNDEFINED

Document #: 38-05357 Rev. *G

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Contents Description 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1441AV33 1M x Logic Block Diagram CY7C1443AV33 2MxLogic Block Diagram CY7C1447AV33 512K x BWE Enable CE1 Register CE2 CE3CY7C1443AV33 2M x Pin ConfigurationsCY7C1441AV33 Adsp TDI TDO ModeBWE Adsc ADV DQP CDQ B DQP G DQP C DQ G DQ BDQ G DQP DQ CByte Write Select Inputs, Active LOW. Qualified with Pin DefinitionsName Description Ground for the Core of the Device Power Supply Inputs to the Core of the DevicePower Supply for the IO Circuitry Ground for the IO CircuitryLinear Burst Address Table Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsTruth Table Cycle DescriptionFunction CY7C1441AV33 2 Partial Truth Table for Read/WriteTruth Table for Read/Write Function CY7C1443AV33TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set Instruction RegisterTAP Timing ExtestParameter Description Min Max Unit Clock TAP AC Switching CharacteristicsSetup Times Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Parameter Description Conditions Min Max UnitIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBit # Ball ID Ball Fbga Boundary Scan Order13,14CY7C1441AV33 1M x 36, CY7C1443AV33 2M x Bit # Ball ID Maximum Ratings Electrical Characteristics Over the Operating Range15DC Electrical Characteristics Over the Operating Range Operating RangeCapacitance Thermal ResistanceOutput Times Switching Characteristics100 Unit Parameter Min Max Data Out Q High-Z QA1 Timing DiagramsAdsp Adsc ADV suspends burstWrite Cycle Timing24 Read/Write Cycle Timing24, 26 ZZ Mode Timing28 Ordering Information Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x1.76 mm SYT Issue Date Orig. Description of ChangeCJM VKN/AESA RXUVKN
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