Cypress CY7C1441AV33 Dq G Dq B, Dq B Dqp G Dqp C, Dqp Dq C, Dq F Dq C, Dq H, DQ a DQ H, DQ a DQP

Page 6

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Pin Configurations (continued)

209-ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1447AV33 (512K × 72)

1

2

3

4

5

6

7

8

9

10

11

A

DQG

DQ

A

CE

A

DQ

DQB

2

ADSP

ADSC

ADV

CE

3

G

B

DQG

A

DQB

C

G

NC288M

BWS

F

BWS

BW

B

BWS

C

DQG

NC/144M

1

NC/576M

DQB

BWS

H

BWS

D

CE

BWS

E

BWS

A

D

DQG

VSS

NC/1G

NC

OE

GW

VSS

DQB

E

DQPG

DQPC

VDDQ

VDD

VDDQ

DQP

F

B

F

DQC

VSS

NC

VSS

DQF

G

DQC

VDDQ

VDD

NC

VDD

VDDQ

DQF

H

DQC

VSS

NC

VSS

DQF

J

DQC

VDDQ

VDD

NC

VDD

VDDQ

DQF

K

NC

CLK

NC

VSS

NC

L

DQH

VDDQ

VDD

NC

VDD

VDDQ

DQA

M

DQH

VSS

NC

VSS

DQA

N

DQH

VDDQ

VDD

NC

VDD

VDDQ

DQA

P

DQH

VSS

ZZ

VSS

DQA

R

DQP

H

VDDQ

V

DDQ

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

DQP

D

E

A

T

DQD

VSS

NC

MODE

NC

VSS

DQE

U

DQ

DQD

NC/72M

A

DQE

D

V

DQD

A

A1

A

DQE

W

DQD

TMS

TDI

A

A0

A

TDO

TCK

DQE

Document #: 38-05357 Rev. *G

Page 6 of 31

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Contents Description 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1441AV33 1M x Logic Block Diagram CY7C1443AV33 2MxLogic Block Diagram CY7C1447AV33 512K x BWE Enable CE1 Register CE2 CE3Pin Configurations CY7C1441AV33CY7C1443AV33 2M x Adsp TDI TDO ModeBWE Adsc ADV DQP CDQ B DQP G DQP C DQ G DQ BDQ G DQP DQ CPin Definitions Name DescriptionByte Write Select Inputs, Active LOW. Qualified with Ground for the Core of the Device Power Supply Inputs to the Core of the DevicePower Supply for the IO Circuitry Ground for the IO CircuitryInterleaved Burst Address Table Mode = Floating or VDD Functional OverviewLinear Burst Address Table Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsTruth Table Cycle DescriptionFunction CY7C1441AV33 2 Partial Truth Table for Read/WriteTruth Table for Read/Write Function CY7C1443AV33TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set Instruction RegisterTAP Timing ExtestParameter Description Min Max Unit Clock TAP AC Switching CharacteristicsSetup Times Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Parameter Description Conditions Min Max UnitIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall Fbga Boundary Scan Order13,14 CY7C1441AV33 1M x 36, CY7C1443AV33 2M x Bit # Ball IDBit # Ball ID Maximum Ratings Electrical Characteristics Over the Operating Range15DC Electrical Characteristics Over the Operating Range Operating RangeCapacitance Thermal ResistanceSwitching Characteristics 100 Unit Parameter Min MaxOutput Times Data Out Q High-Z QA1 Timing DiagramsAdsp Adsc ADV suspends burstWrite Cycle Timing24 Read/Write Cycle Timing24, 26 ZZ Mode Timing28 Ordering Information Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x1.76 mm Issue Date Orig. Description of Change CJMSYT RXU VKNVKN/AESA