Cypress CY7C1441AV33, CY7C1443AV33, CY7C1447AV33 Ball Fbga Boundary Scan Order13,14, Bit # Ball ID

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

165-ball FBGA Boundary Scan Order[13,14]

CY7C1441AV33 (1M x 36), CY7C1443AV33 (2M x 18)

Bit #

Ball ID

1N6

2N7

3N10

4P11

5P8

6R8

7R9

8P9

9P10

10R10

11R11

12H11

13N11

14M11

15L11

16K11

17J11

18M10

19L10

20K10

21J10

22H9

23H10

24G11

25F11

Bit #

Ball ID

26E11

27D11

28G10

29F10

30E10

31D10

32C11

33A11

34B11

35A10

36B10

37A9

38B9

39C10

40A8

41B8

42A7

43B7

44B6

45A6

46B5

47A5

48A4

49B4

50B3

Bit #

Ball ID

51A3

52A2

53B2

54C2

55B1

56A1

57C1

58D1

59E1

60F1

61G1

62D2

63E2

64F2

65G2

66H1

67H3

68J1

69K1

70L1

71M1

72J2

73K2

74L2

75M2

Bit #

Ball ID

76N1

77N2

78P1

79R1

80R2

81P3

82R3

83P2

84R4

85P4

86N5

87P6

88R6

89Internal

Notes

13.Balls which are NC (No Connect) are preset LOW.

14.Bit# 89 is preset HIGH.

Document #: 38-05357 Rev. *G

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Contents Description 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1441AV33 1M x Logic Block Diagram CY7C1443AV33 2MxLogic Block Diagram CY7C1447AV33 512K x BWE Enable CE1 Register CE2 CE3Pin Configurations CY7C1441AV33CY7C1443AV33 2M x Adsp TDI TDO ModeBWE Adsc ADV DQP CDQ B DQP G DQP C DQ G DQ BDQ G DQP DQ CPin Definitions Name DescriptionByte Write Select Inputs, Active LOW. Qualified with Ground for the Core of the Device Power Supply Inputs to the Core of the DevicePower Supply for the IO Circuitry Ground for the IO CircuitryInterleaved Burst Address Table Mode = Floating or VDD Functional OverviewLinear Burst Address Table Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsTruth Table Cycle DescriptionFunction CY7C1441AV33 2 Partial Truth Table for Read/WriteTruth Table for Read/Write Function CY7C1443AV33TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set Instruction RegisterTAP Timing ExtestParameter Description Min Max Unit Clock TAP AC Switching CharacteristicsSetup Times Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Parameter Description Conditions Min Max UnitIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall Fbga Boundary Scan Order13,14 CY7C1441AV33 1M x 36, CY7C1443AV33 2M x Bit # Ball IDBit # Ball ID Maximum Ratings Electrical Characteristics Over the Operating Range15DC Electrical Characteristics Over the Operating Range Operating RangeCapacitance Thermal ResistanceSwitching Characteristics 100 Unit Parameter Min MaxOutput Times Data Out Q High-Z QA1 Timing DiagramsAdsp Adsc ADV suspends burstWrite Cycle Timing24 Read/Write Cycle Timing24, 26 ZZ Mode Timing28 Ordering Information Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x1.76 mm Issue Date Orig. Description of Change CJMSYT RXU VKNVKN/AESA