Cypress CY7C1443AV33 manual 3V TAP AC Test Conditions, 5V TAP AC Test Conditions, GND VIN Vddq

Page 16

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

3.3V TAP AC Test Conditions

Input pulse levels

VSS to 3.3V

Input rise and fall times

1 ns

Input timing reference levels

1.5V

Output reference levels

1.5V

Test load termination supply voltage

1.5V

2.5V TAP AC Test Conditions

Input pulse levels

VSS to 2.5V

Input rise and fall time

1 ns

Input timing reference levels

1.25V

Output reference levels

1.25V

Test load termination supply voltage

1.25V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Output Load Equivalent

 

 

 

 

 

 

1.5V

 

 

 

 

 

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

50Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50Ω

TDO

 

 

 

 

 

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZO = 50 Ω

 

 

 

 

 

20p F

 

 

 

 

 

ZO = 50 Ω

 

 

 

 

 

 

 

20p F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TAP DC Electrical Characteristics And Operating Conditions

 

 

 

 

 

 

 

 

 

 

 

 

 

(0°C < TA < +70°C; V = 3.135V to 3.6V unless otherwise noted)[11]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

Description

 

 

 

 

 

Description

Conditions

 

 

 

Min.

 

 

Max.

 

Unit

VOH1

 

Output HIGH Voltage

 

IOH = –4.0 mA

VDDQ = 3.3V

 

2.4

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

IOH = –1.0 mA

VDDQ = 2.5V

 

 

2.0

 

 

 

 

 

 

 

 

 

 

V

VOH2

 

Output HIGH Voltage

 

IOH = –100 µA

VDDQ = 3.3V

 

 

2.9

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

 

2.1

 

 

 

 

 

 

 

 

 

 

V

VOL1

 

Output LOW Voltage

 

IOL = 8.0 mA

VDDQ = 3.3V

 

 

 

 

0.4

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

IOL = 1.0 mA

VDDQ = 2.5V

 

 

 

 

0.4

 

 

 

 

 

 

 

V

VOL2

 

Output LOW Voltage

 

IOL = 100 µA

VDDQ = 3.3V

 

 

 

 

0.2

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

 

 

 

0.2

 

 

 

 

 

 

 

V

VIH

 

Input HIGH Voltage

 

 

 

 

 

 

VDDQ = 3.3V

 

 

2.0

VDD + 0.3

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

 

1.7

VDD + 0.3

 

V

VIL

 

Input LOW Voltage

 

 

 

 

 

 

VDDQ = 3.3V

 

 

 

–0.3

0.8

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

 

 

–0.3

0.7

 

 

 

 

 

 

 

V

IX

 

Input Load Current

 

GND < VIN < VDDQ

 

 

 

 

 

–5

5

 

 

 

 

 

 

 

µA

Note

11. All voltages referenced to VSS (GND).

Document #: 38-05357 Rev. *G

Page 16 of 31

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Contents Features Selection Guide Functional DescriptionDescription 133 MHz 100 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1441AV33 1M x Logic Block Diagram CY7C1443AV33 2MxLogic Block Diagram CY7C1447AV33 512K x BWE Enable CE1 Register CE2 CE3CY7C1441AV33 Pin ConfigurationsCY7C1443AV33 2M x TDI TDO Mode BWE Adsc ADVAdsp DQP CDQ G DQ B DQ GDQ B DQP G DQP C DQP DQ CName Description Pin DefinitionsByte Write Select Inputs, Active LOW. Qualified with Power Supply Inputs to the Core of the Device Power Supply for the IO CircuitryGround for the Core of the Device Ground for the IO CircuitryFunctional Overview Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table ZZ Mode Electrical Characteristics Truth TableParameter Description Test Conditions Min Max Unit Cycle DescriptionPartial Truth Table for Read/Write Truth Table for Read/WriteFunction CY7C1441AV33 2 Function CY7C1443AV33TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set Instruction RegisterTAP Timing ExtestTAP AC Switching Characteristics Setup TimesParameter Description Min Max Unit Clock Hold TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Parameter Description Conditions Min Max UnitIdentification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeCY7C1441AV33 1M x 36, CY7C1443AV33 2M x Bit # Ball ID Ball Fbga Boundary Scan Order13,14Bit # Ball ID Electrical Characteristics Over the Operating Range15 DC Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeCapacitance Thermal Resistance100 Unit Parameter Min Max Switching CharacteristicsOutput Times Timing Diagrams Adsp AdscData Out Q High-Z QA1 ADV suspends burstWrite Cycle Timing24 Read/Write Cycle Timing24, 26 ZZ Mode Timing28 Ordering Information Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x1.76 mm CJM Issue Date Orig. Description of ChangeSYT VKN RXUVKN/AESA