Cypress CY7C1443AV33, CY7C1441AV33, CY7C1447AV33 Maximum Ratings, Operating Range, Range Ambient

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Storage Temperature

–65°C to +150°C

Ambient Temperature with

 

 

Power Applied

–55°C to +125°C

Supply Voltage on VDD Relative to GND

–0.3V to +4.6V

Supply Voltage on VDDQ Relative to GND

–0.3V to +VDD

DC Voltage Applied to Outputs

 

 

in Tri-State

–0.5V to VDDQ + 0.5V

DC Input Voltage

–0.5V to VDD + 0.5V

Current into Outputs (LOW)

 

20 mA

Static Discharge Voltage

 

>2001V

(per MIL-STD-883, Method 3015)

 

Latch-up Current

 

>200 mA

Operating Range

 

 

 

 

 

 

Range

Ambient

VDD

VDDQ

Temperature

Commercial

0°C to +70°C

3.3V –5%/+10%

2.5V –5%

 

 

 

to VDD

Industrial

–40°C to +85°C

 

Electrical Characteristics Over the Operating Range[15, 16]

DC Electrical Characteristics Over the Operating Range

Parameter

Description

 

 

 

Test Conditions

Min.

Max.

Unit

VDD

Power Supply Voltage

 

 

 

 

 

 

 

 

3.135

3.6

V

VDDQ

IO Supply Voltage

for 3.3V IO

 

 

 

 

 

3.135

VDD

V

 

 

for 2.5V IO

 

 

 

 

 

2.375

2.625

V

 

 

 

 

 

 

 

VOH

Output HIGH Voltage

for 3.3V IO, IOH = –4.0 mA

 

2.4

 

V

 

 

for 2.5V IO, IOH = –1.0 mA

 

2.0

 

V

VOL

Output LOW Voltage

for 3.3V IO, IOL = 8.0 mA

 

 

 

0.4

V

 

 

for 2.5V IO, IOL = 1.0 mA

 

 

 

0.4

V

VIH

Input HIGH Voltage[15]

for 3.3V IO

 

 

 

 

 

2.0

VDD + 0.3V

V

 

 

for 2.5V IO

 

 

 

 

 

1.7

VDD + 0.3V

V

VIL

Input LOW Voltage[15]

for 3.3V IO

 

 

 

 

 

–0.3

0.8

V

 

 

for 2.5V IO

 

 

 

 

 

–0.3

0.7

V

 

 

 

 

 

 

 

 

 

 

 

IX

Input Leakage Current

GND VI VDDQ

 

 

 

 

 

–5

5

μA

 

except ZZ and MODE

 

 

 

 

 

 

 

 

 

 

 

 

Input Current of MODE

Input = VSS

 

 

 

 

 

–30

 

μA

 

 

Input = VDD

 

 

 

 

 

 

5

μA

 

Input Current of ZZ

Input = VSS

 

 

 

 

 

–5

 

μA

 

 

Input = VDD

 

 

 

 

 

 

30

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

 

–5

5

μA

IDD

VDD Operating Supply

VDD = Max., IOUT = 0 mA,

7.5-ns cycle, 133 MHz

 

310

mA

 

Current

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

 

 

 

 

 

 

10-ns cycle, 100 MHz

 

290

mA

ISB1

Automatic CE

Max. VDD, Device Deselected,

All Speeds

 

180

mA

 

Power down

VIN

VIH or VIN VIL, f = fMAX,

 

 

 

 

 

Current—TTL Inputs

inputs switching

 

 

 

 

 

 

 

 

I

Automatic CE

Max. V

, Device Deselected,

All speeds

 

120

mA

SB2

Power down

V

V DD – 0.3V or V

 

0.3V,

 

 

 

 

 

Current—CMOS Inputs

IN

DD

 

IN

 

 

 

 

 

 

 

f = 0, inputs static

 

 

 

 

 

 

 

 

I

Automatic CE

Max. V

, Device Deselected,

All Speeds

 

180

mA

SB3

Power down

V

V DD – 0.3V or V

IN

0.3V,

 

 

 

 

 

Current—CMOS Inputs

IN

DDQ

 

 

 

 

 

 

 

f = fMAX, inputs switching

 

 

 

 

 

ISB4

Automatic CE

Max. VDD, Device Deselected,

All Speeds

 

135

mA

 

Power down

VIN

VDD

– 0.3V or VIN 0.3V,

 

 

 

 

 

Current—TTL Inputs

f = 0, inputs static

 

 

 

 

 

 

 

 

Notes

15.Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).

16.TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

Document #: 38-05357 Rev. *G

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesSelection Guide Functional Description Description 133 MHz 100 MHz UnitLogic Block Diagram CY7C1443AV33 2Mx Logic Block Diagram CY7C1441AV33 1M xBWE Enable CE1 Register CE2 CE3 Logic Block Diagram CY7C1447AV33 512K xCY7C1441AV33 Pin ConfigurationsCY7C1443AV33 2M x DQP C TDI TDO ModeBWE Adsc ADV AdspDQP DQ C DQ G DQ BDQ G DQ B DQP G DQP CName Description Pin DefinitionsByte Write Select Inputs, Active LOW. Qualified with Ground for the IO Circuitry Power Supply Inputs to the Core of the DevicePower Supply for the IO Circuitry Ground for the Core of the DeviceFunctional Overview Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Cycle Description ZZ Mode Electrical CharacteristicsTruth Table Parameter Description Test Conditions Min Max UnitFunction CY7C1443AV33 Partial Truth Table for Read/WriteTruth Table for Read/Write Function CY7C1441AV33 2Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramInstruction Register TAP Instruction SetExtest TAP TimingHold Times TAP AC Switching CharacteristicsSetup Times Parameter Description Min Max Unit ClockParameter Description Conditions Min Max Unit TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Identification CodesCY7C1441AV33 1M x 36, CY7C1443AV33 2M x Bit # Ball ID Ball Fbga Boundary Scan Order13,14Bit # Ball ID Operating Range Electrical Characteristics Over the Operating Range15DC Electrical Characteristics Over the Operating Range Maximum RatingsThermal Resistance Capacitance100 Unit Parameter Min Max Switching CharacteristicsOutput Times ADV suspends burst Timing DiagramsAdsp Adsc Data Out Q High-Z QA1Write Cycle Timing24 Read/Write Cycle Timing24, 26 ZZ Mode Timing28 Ordering Information Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x1.76 mm CJM Issue Date Orig. Description of ChangeSYT VKN RXUVKN/AESA