Cypress CY7C1443AV33, CY7C1441AV33, CY7C1447AV33 manual Rxu, Vkn/Aesa

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CY7C1441AV33

 

 

 

 

 

 

CY7C1443AV33,CY7C1447AV33

 

 

 

 

 

 

 

 

 

 

 

Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

Document Number: 38-05357

 

 

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

Change

*E

417547

See ECN

RXU

Converted from Preliminary to Final.

 

 

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901

 

 

 

 

 

 

North First Street” to “198 Champion Court”.

 

 

 

 

 

 

Changed IX current value in MODE from –5 & 30 μA to –30 & 5 μA respectively

 

 

 

 

 

 

and also Changed IX current value in ZZ from –30 & 5 μA to –5 & 30 μA respec-

 

 

 

 

 

 

tively on page# 19.

 

 

 

 

 

 

Modified test condition in note# 8 from VIH < VDD to VIH < VDD.

 

 

 

 

 

 

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

 

 

 

 

 

 

Electrical Characteristics Table.

 

 

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

 

 

Information table.

 

 

 

 

 

 

Replaced Package Diagram of 51-85050 from *A to *B

 

 

 

 

 

 

Updated the Ordering Information.

*F

473650

See ECN

VKN

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

 

 

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC

 

 

 

 

 

 

Switching Characteristics table.

 

 

 

 

 

 

Updated the Ordering Information table.

*G

2447027

See ECN

VKN/AESA

Corrected typo in the Ordering Information table

 

 

 

 

 

 

Corrected typo in the CY7C1447AV33 ‘s Logic Block diagram

 

 

 

 

 

 

Updated the x72 block diagram

 

 

 

 

 

 

 

© Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 38-05357 Rev. *G

Revised May 09, 2008

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i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesSelection Guide Functional Description Description 133 MHz 100 MHz UnitLogic Block Diagram CY7C1443AV33 2Mx Logic Block Diagram CY7C1441AV33 1M xBWE Enable CE1 Register CE2 CE3 Logic Block Diagram CY7C1447AV33 512K xCY7C1441AV33 Pin ConfigurationsCY7C1443AV33 2M x DQP C TDI TDO ModeBWE Adsc ADV AdspDQP DQ C DQ G DQ BDQ G DQ B DQP G DQP CName Description Pin DefinitionsByte Write Select Inputs, Active LOW. Qualified with Ground for the IO Circuitry Power Supply Inputs to the Core of the DevicePower Supply for the IO Circuitry Ground for the Core of the DeviceFunctional Overview Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Cycle Description ZZ Mode Electrical CharacteristicsTruth Table Parameter Description Test Conditions Min Max UnitFunction CY7C1443AV33 Partial Truth Table for Read/WriteTruth Table for Read/Write Function CY7C1441AV33 2Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramInstruction Register TAP Instruction SetExtest TAP TimingHold Times TAP AC Switching CharacteristicsSetup Times Parameter Description Min Max Unit ClockParameter Description Conditions Min Max Unit TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Identification CodesCY7C1441AV33 1M x 36, CY7C1443AV33 2M x Bit # Ball ID Ball Fbga Boundary Scan Order13,14Bit # Ball ID Operating Range Electrical Characteristics Over the Operating Range15DC Electrical Characteristics Over the Operating Range Maximum RatingsThermal Resistance Capacitance100 Unit Parameter Min Max Switching CharacteristicsOutput Times ADV suspends burst Timing DiagramsAdsp Adsc Data Out Q High-Z QA1Write Cycle Timing24 Read/Write Cycle Timing24, 26 ZZ Mode Timing28 Ordering Information Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x1.76 mm CJM Issue Date Orig. Description of ChangeSYT VKN RXUVKN/AESA