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| CY7C1441AV33 | |
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| CY7C1443AV33,CY7C1447AV33 | ||||
Logic Block Diagram – CY7C1441AV33 (1M x 36) |
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A 0, A1, A |
| ADDRESS |
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| REGISTER |
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MODE |
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ADV |
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| BURST | Q1 |
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CLK |
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| COUNTER |
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| AND LOGIC | Q0 |
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| CLR |
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ADSC |
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ADSP |
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| DQ D, DQP D |
| DQ D, DQP D |
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BW D |
| BYTE |
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BYTE |
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| WRITE REGISTER |
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| WRITE REGISTER |
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| DQ C, DQP C |
| DQ C, DQP C |
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BW C |
| BYTE |
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BYTE |
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| WRITE REGISTER |
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| WRITE REGISTER |
| MEMORY |
| OUTPUT | DQ s | ||
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| SENSE | |||||
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| ARRAY | BUFFERS | DQP A | |
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| DQ B, DQP B | AMPS | |||
| DQ B, DQP B |
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| DQP B | |||
BW B |
| BYTE |
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| DQP C | ||
BYTE |
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| WRITE REGISTER |
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| DQP D | |
| WRITE REGISTER |
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| DQ A , DQP A |
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BW A | DQ A , | DQPA |
| BYTE |
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BYTE |
| WRITE REGISTER |
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BWE |
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WRITE REGISTER |
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GW |
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| INPUT |
CE1 |
| ENABLE |
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REGISTER |
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CE2 |
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CE3 |
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OE |
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ZZ | SLEEP |
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CONTROL |
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Logic Block Diagram – CY7C1443AV33 (2Mx 18) |
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A0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BW B
BW A
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
A[1:0]
BURST | Q1 |
COUNTER AND | |
LOGIC |
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CLR | Q0 |
DQ B,DQP B |
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WRITE REGISTER |
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DQ A,DQP A |
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WRITE REGISTER |
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ENABLE |
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REGISTER |
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DQ B,DQP B WRITE DRIVER
DQ A,DQP A WRITE DRIVER
MEMORY
ARRAY
SENSE AMPS
OUTPUT | DQs |
BUFFERS | DQP A |
| DQP B |
| INPUT |
| REGISTERS |
ZZ
SLEEP
CONTROL
Document #: | Page 2 of 31 |
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