Cypress CY7C1441AV33, CY7C1443AV33, CY7C1447AV33 Issue Date Orig. Description of Change, Cjm, Syt

Page 30

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Document History Page

Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM

Document Number: 38-05357

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

124459

03/06/03

CJM

New Data Sheet

 

 

 

 

 

*A

254910

See ECN

SYT

Part number changed from previous revision. New and old part number differ by

 

 

 

 

the letter “A”

 

 

 

 

Modified Functional Block diagrams

 

 

 

 

Modified switching waveforms

 

 

 

 

Added Footnote #13 (32-Bit Vendor I.D Code changed)

 

 

 

 

Added Boundary scan information

 

 

 

 

Added IDD, IX and ISB values in the DC Electrical Characteristics

 

 

 

 

Added tPOWER specifications in Switching Characteristics table

 

 

 

 

Removed 119 PBGA Package

 

 

 

 

Changed 165 FBGA Package from BB165C (15 x 17 x 1.20 mm) to BB165

 

 

 

 

(15 x 17 x 1.40 mm)

 

 

 

 

Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A

 

 

 

 

(14 x 22 x 1.76 mm)

*B

300131

See ECN

SYT

Removed 150 and 117 MHz Speed Bins

 

 

 

 

Changed ΘJA and ΘJC from TBD to 25.21 and 2.58 °C/W respectively for TQFP

 

 

 

 

Package on Pg # 21

 

 

 

 

Added lead-free information for 100-pin TQFP, 165 FBGA and 209 BGA

 

 

 

 

Packages.

 

 

 

 

Added comment of ‘Lead-free BG and BZ packages availability’ below the

 

 

 

 

Ordering Information

*C

320813

See ECN

SYT

Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA

 

 

 

 

Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical

 

 

 

 

Characteristics table.

 

 

 

 

Replaced the TBD’s for IDD, ISB1, ISB2, ISB3 and ISB4 to their respective values.

 

 

 

 

Replaced TBD’s for ΘJA and ΘJC to their respective values for 165 fBGA and 209

 

 

 

 

fBGA packages on the Thermal Resistance table.

 

 

 

 

Changed CIN,CCLK and CIO to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP

 

 

 

 

Package.

 

 

 

 

Removed “Lead-free BG and BZ packages availability” comment below the

 

 

 

 

Ordering Information

*D

331551

See ECN

SYT

Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA

 

 

 

 

Packages as per JEDEC standards and updated the Pin Definitions accordingly

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Replaced TBD to 100 mA for IDDZZ

 

 

 

 

Changed CIN, CCLK and CIO to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA

 

 

 

 

Package.

 

 

 

 

Added Industrial Temperature Grade

 

 

 

 

Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively

 

 

 

 

Updated the Ordering Information by shading and unshading MPNs as per avail-

 

 

 

 

ability

Document #: 38-05357 Rev. *G

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Contents Description 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1441AV33 1M x Logic Block Diagram CY7C1443AV33 2MxLogic Block Diagram CY7C1447AV33 512K x BWE Enable CE1 Register CE2 CE3Pin Configurations CY7C1441AV33CY7C1443AV33 2M x Adsp TDI TDO ModeBWE Adsc ADV DQP CDQ B DQP G DQP C DQ G DQ BDQ G DQP DQ CPin Definitions Name DescriptionByte Write Select Inputs, Active LOW. Qualified with Ground for the Core of the Device Power Supply Inputs to the Core of the DevicePower Supply for the IO Circuitry Ground for the IO CircuitryInterleaved Burst Address Table Mode = Floating or VDD Functional OverviewLinear Burst Address Table Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsTruth Table Cycle DescriptionFunction CY7C1441AV33 2 Partial Truth Table for Read/WriteTruth Table for Read/Write Function CY7C1443AV33TAP Controller State Diagram Ieee 1149.1 Serial Boundary Scan JtagTAP Instruction Set Instruction RegisterTAP Timing ExtestParameter Description Min Max Unit Clock TAP AC Switching CharacteristicsSetup Times Hold Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Parameter Description Conditions Min Max UnitIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall Fbga Boundary Scan Order13,14 CY7C1441AV33 1M x 36, CY7C1443AV33 2M x Bit # Ball IDBit # Ball ID Maximum Ratings Electrical Characteristics Over the Operating Range15DC Electrical Characteristics Over the Operating Range Operating RangeCapacitance Thermal ResistanceSwitching Characteristics 100 Unit Parameter Min MaxOutput Times Data Out Q High-Z QA1 Timing DiagramsAdsp Adsc ADV suspends burstWrite Cycle Timing24 Read/Write Cycle Timing24, 26 ZZ Mode Timing28 Ordering Information Package Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x1.76 mm Issue Date Orig. Description of Change CJMSYT RXU VKNVKN/AESA
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