Cypress CY7C1443AV33, CY7C1441AV33, CY7C1447AV33 manual Pin Definitions, Name Description

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CY7C1441AV33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1443AV33,CY7C1447AV33

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

IO

 

 

Description

 

 

 

A0, A1, A

 

 

Input-

Address Inputs Used to Select One of the Address Locations. Sampled

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and CE3 are sampled active. A[1:0] feed the 2-bit counter.

 

 

 

 

 

A,

 

 

 

B

 

 

Input-

Byte Write Select Inputs, Active LOW. Qualified with

 

to conduct byte

 

 

BW

BW

 

 

BWE

 

BWC, BWD,

Synchronous

writes to the SRAM. Sampled on the rising edge of CLK.

 

 

BWE, BWF,

 

 

 

 

 

 

 

 

 

 

 

BWG, BWH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Global Write Enable Input, Active LOW. When asserted LOW on the rising

 

 

GW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

edge of CLK, a global write is conducted (ALL bytes are written, regardless

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

of the values on BWX and BWE).

 

 

CLK

 

 

Input-

Clock Input. Used to capture all synchronous inputs to the device. Also used

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

to increment the burst counter when ADV is asserted LOW, during a burst

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

operation.

 

 

 

1

 

 

 

 

 

 

Input-

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

in conjunction with CE2 and CE3 to select/deselect the device. ADSP is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ignored if CE1 is HIGH. CE1 is sampled only when a new external address is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

loaded.

 

 

CE2

 

 

Input-

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

only when a new external address is loaded.

 

 

 

3

 

 

 

 

 

 

Input-

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

in conjunction with CE1 and CE2 to select/deselect the device. CE3 is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

assumed active throughout this document for BGA. CE3 is sampled only when

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a new external address is loaded.

 

 

 

 

 

 

 

 

 

 

 

Input-

Output Enable, Asynchronous Input, Active LOW. Controls the direction

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Asynchronous

of the IO pins. When LOW, the IO pins behave as outputs. When deasserted

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the first clock of a read cycle when emerging from a deselected state.

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Advance Input Signal, Sampled on the Rising Edge of CLK. When

 

 

ADV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

asserted, it automatically increments the address in a burst cycle.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Address Strobe from Processor, Sampled on the Rising Edge of CLK,

 

 

ADSP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

Active LOW. When asserted LOW, addresses presented to the device are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

captured in the address registers. A[1:0] are also loaded into the burst counter.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is ignored when

CE

1 is deasserted HIGH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Address Strobe from Controller, Sampled on the Rising Edge of CLK,

 

 

ADSC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

Active LOW. When asserted LOW, addresses presented to the device are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

captured in the address registers. A[1:0] are also loaded into the burst counter.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When ADSP and ADSC are both asserted, only ADSP is recognized.

 

 

 

 

 

 

 

 

 

 

 

Input-

Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK.

 

 

BWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

This signal must be asserted LOW to conduct a byte write.

 

 

ZZ

 

 

Input-

ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Asynchronous

a non-time-critical “sleep” condition with data integrity preserved. For normal

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

operation, this pin must be LOW or left floating. ZZ pin has an internal pull

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

down.

 

Document #: 38-05357 Rev. *G

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesSelection Guide Functional Description Description 133 MHz 100 MHz UnitLogic Block Diagram CY7C1443AV33 2Mx Logic Block Diagram CY7C1441AV33 1M xBWE Enable CE1 Register CE2 CE3 Logic Block Diagram CY7C1447AV33 512K xCY7C1441AV33 Pin ConfigurationsCY7C1443AV33 2M x DQP C TDI TDO ModeBWE Adsc ADV AdspDQP DQ C DQ G DQ BDQ G DQ B DQP G DQP CName Description Pin DefinitionsByte Write Select Inputs, Active LOW. Qualified with Ground for the IO Circuitry Power Supply Inputs to the Core of the DevicePower Supply for the IO Circuitry Ground for the Core of the DeviceFunctional Overview Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Cycle Description ZZ Mode Electrical CharacteristicsTruth Table Parameter Description Test Conditions Min Max UnitFunction CY7C1443AV33 Partial Truth Table for Read/WriteTruth Table for Read/Write Function CY7C1441AV33 2Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramInstruction Register TAP Instruction SetExtest TAP TimingHold Times TAP AC Switching CharacteristicsSetup Times Parameter Description Min Max Unit ClockParameter Description Conditions Min Max Unit TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Identification CodesCY7C1441AV33 1M x 36, CY7C1443AV33 2M x Bit # Ball ID Ball Fbga Boundary Scan Order13,14Bit # Ball ID Operating Range Electrical Characteristics Over the Operating Range15DC Electrical Characteristics Over the Operating Range Maximum RatingsThermal Resistance Capacitance100 Unit Parameter Min Max Switching CharacteristicsOutput Times ADV suspends burst Timing DiagramsAdsp Adsc Data Out Q High-Z QA1Write Cycle Timing24 Read/Write Cycle Timing24, 26 ZZ Mode Timing28 Ordering Information Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x1.76 mm CJM Issue Date Orig. Description of ChangeSYT VKN RXUVKN/AESA
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