Cypress CY7C1441AV33 manual Switching Characteristics, Unit Parameter Min Max, Output Times

Page 21

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Switching Characteristics

Over the Operating Range[22, 23]

 

 

 

 

 

 

 

 

 

 

 

 

Description

–133

 

–100

 

Unit

Parameter

 

 

 

 

 

 

 

 

 

 

 

Min.

 

Max.

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

V

DD

(Typical) to the first Access[18]

1

 

 

1

 

 

ms

POWER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

Clock Cycle Time

7.5

 

 

10

 

 

ns

tCH

Clock HIGH

2.5

 

 

3.0

 

 

ns

tCL

Clock LOW

2.5

 

 

3.0

 

 

ns

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCDV

Data Output Valid After CLK Rise

 

 

6.5

 

 

8.5

ns

tDOH

Data Output Hold After CLK Rise

2.5

 

 

2.5

 

 

ns

tCLZ

Clock to Low-Z[19, 20, 21]

2.5

 

 

2.5

 

 

ns

tCHZ

Clock to High-Z[19, 20, 21]

 

 

3.8

0

 

4.5

ns

tOEV

 

 

 

LOW to Output Valid

 

 

3.0

 

 

3.8

ns

OE

 

 

 

 

tOELZ

 

 

 

LOW to Output Low-Z[19, 20, 21]

0

 

 

0

 

 

ns

OE

 

 

tOEHZ

 

 

 

HIGH to Output High-Z[19, 20, 21]

 

 

3.0

 

 

4.0

ns

OE

 

 

 

 

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

Address Setup Before CLK Rise

1.5

 

 

1.5

 

 

ns

tADS

 

 

 

 

 

 

 

 

 

 

Setup Before CLK Rise

1.5

 

 

1.5

 

 

ns

ADSP,

ADSC

 

 

tADVS

 

 

 

 

 

Setup Before CLK Rise

1.5

 

 

1.5

 

 

ns

ADV

 

 

tWES

 

 

 

 

 

 

 

 

 

 

X Setup Before CLK Rise

1.5

 

 

1.5

 

 

ns

GW,

BWE,

BW

 

 

tDS

Data Input Setup Before CLK Rise

1.5

 

 

1.5

 

 

ns

tCES

Chip Enable Setup

1.5

 

 

1.5

 

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAH

Address Hold After CLK Rise

0.5

 

 

0.5

 

 

ns

tADH

 

 

 

 

 

 

 

 

 

 

Hold After CLK Rise

0.5

 

 

0.5

 

 

ns

ADSP,

ADSC

 

 

tWEH

 

 

 

 

 

 

 

 

 

 

X Hold After CLK Rise

0.5

 

 

0.5

 

 

ns

GW,

BWE,

BW

 

 

tADVH

 

 

 

 

Hold After CLK Rise

0.5

 

 

0.5

 

 

ns

ADV

 

 

tDH

Data Input Hold After CLK Rise

0.5

 

 

0.5

 

 

ns

tCEH

Chip Enable Hold After CLK Rise

0.5

 

 

0.5

 

 

ns

Notes

18.This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation can be initiated.

19.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 20. Transition is measured ± 200 mV from steady-state voltage.

20.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

21.This parameter is sampled and not 100% tested.

22.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

23.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05357 Rev. *G

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Contents Selection Guide Functional Description FeaturesDescription 133 MHz 100 MHz Unit Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1443AV33 2Mx Logic Block Diagram CY7C1441AV33 1M xBWE Enable CE1 Register CE2 CE3 Logic Block Diagram CY7C1447AV33 512K xPin Configurations CY7C1441AV33CY7C1443AV33 2M x BWE Adsc ADV TDI TDO ModeAdsp DQP CDQ G DQ G DQ BDQ B DQP G DQP C DQP DQ CPin Definitions Name DescriptionByte Write Select Inputs, Active LOW. Qualified with Power Supply for the IO Circuitry Power Supply Inputs to the Core of the DeviceGround for the Core of the Device Ground for the IO CircuitryInterleaved Burst Address Table Mode = Floating or VDD Functional OverviewLinear Burst Address Table Truth Table ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Cycle DescriptionTruth Table for Read/Write Partial Truth Table for Read/WriteFunction CY7C1441AV33 2 Function CY7C1443AV33Ieee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramInstruction Register TAP Instruction SetExtest TAP TimingSetup Times TAP AC Switching CharacteristicsParameter Description Min Max Unit Clock Hold Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Parameter Description Conditions Min Max UnitScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBall Fbga Boundary Scan Order13,14 CY7C1441AV33 1M x 36, CY7C1443AV33 2M x Bit # Ball IDBit # Ball ID DC Electrical Characteristics Over the Operating Range Electrical Characteristics Over the Operating Range15Maximum Ratings Operating RangeThermal Resistance CapacitanceSwitching Characteristics 100 Unit Parameter Min MaxOutput Times Adsp Adsc Timing DiagramsData Out Q High-Z QA1 ADV suspends burstWrite Cycle Timing24 Read/Write Cycle Timing24, 26 ZZ Mode Timing28 Ordering Information Pin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall Fbga 15 x 17 x 1.4 mm Ball Fbga 14 x 22 x1.76 mm Issue Date Orig. Description of Change CJMSYT RXU VKNVKN/AESA
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