Manuals / Intel / Computer Equipment / Computer Hardware

Intel IXP46X 7.2.4Command Group, TL1 Tpd = 175 ps/in, TL2 Tpd = 175 ps/in, TL3 Tpd = 175 ps/in

Models: IXP45X IXP46X

1 108

Download 108 pages 42.83 Kb

Page 100

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

7.2.4Command Group

The command signal group includes the signals DDRI_MA[13:0], DDRI_BA[1:0], DDRI_RAS, DDRI_CAS and DDRI_WE. The following simulations were constructed for the 2 bank x16 device configuration where each signal would have six receivers.

Table 39 identifies the transmission line lengths for the address (DDRI_MA3) topology shown in Figure 45 and Figure 47. These lengths were chosen as realistic goals given the IXP45X/IXP46X network processors to DDR body to body separation of no more than 500 mils.

Table 39. Command Group Topology Transmission Line Characteristics

Transmission Line	Length

TL1 (Tpd = 175 ps/in)	~ 600 mils
TL2 (Tpd = 175 ps/in)	~ 50 mils
TL3 (Tpd = 175 ps/in)	~ 1,100 mils
TL4 (Tpd = 175 ps/in)	~ 50 mils
TL5, TL8, TL11 (Tpd = 175 ps/in)	~ 800 mils
TL6, TL7, TL9, TL10, TL12, TL13 (Tpd = 175 ps/in)	~ 300 mils

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
100	Document Number: 305261, Revision: 004

Image 100

Intel IXP46X manual 7.2.4Command Group, TL1 Tpd = 175 ps/in, TL2 Tpd = 175 ps/in, TL3 Tpd = 175 ps/in, TL4 Tpd = 175 ps/in

Contents

February Hardware Design GuidelinesDocument No 305261 Revision February Contents IntroductionFebruary 5.0 General Layout and Routing Guide6.0 PCI Interface Design Considerations Document Number 305261, RevisionFigures Tables Revision History DateRevision DescriptionFebruary 1.1Content Overview 1.0Introduction1.2Related Documentation 1.4Overview 1.3Acronyms and AbbreviationsList of Acronyms and Abbreviations 32-bitPCI interface Master/Target 33/66 MHz Figure 1. Intel IXP465 Component Block Diagram MII/SMIICryptography Unit1.5Typical Applications 2.1System Architecture Description 2.0System Architecture2.2System Memory Map JTAG IntelIXP46X ProductLine of Network Processors3.1Soft Fusible Features Signal Type Definitions3.0General Hardware Design Considerations Table3.2.1Signal Interface Soft Fusible Features3.2DDR-266SDRAM Interface DDR SDRAM Interface Pin Description Sheet 1 ofDDR SDRAM Interface Pin Description Sheet 2 of 3.2.2DDR SDRAM Memory Interface 3.3Expansion Bus3.2.3DDR SDRAM Initialization 3.3.2Reset Configuration Straps 3.3.1Signal InterfaceExpansion Bus Signal Recommendations Boot/Reset Strapping Configuration Sheet 1 of TableName Function3.3.38-BitDevice Interface Boot/Reset Strapping Configuration Sheet 2 of3.3.416-BitDevice Interface 3.3.532-BitDevice Interface Byte Access 16-Bit-WordAccess32-Bit-WordAccess 8-BitDeviceByte Access 16-Bit-WordAccess32-Bit-WordAccess 8-BitDeviceIntel Flash 3.3.6Flash InterfaceFigure 5. Flash Interface Example 16-Bit-WordAccess3.4UART Interface 3.3.7SRAM Interface3.3.8Design Notes Figure 6. Expansion Bus SRAM Interface3.4.1Signal Interface UART Signal RecommendationsConnector MII/SMII InterfaceFigure 7. UART Interface Example UART InterfaceMII NPE A Signal Recommendations 3.5.1Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 of MII NPE B Signal Recommendations Sheet 2 of MII NPE C Signal RecommendationsFigure 8. MII Interface Example 3.5.2Device Connection, MII10/100 3.5.3Signal Interface, SMII 3.5.4Device Connection, SMII 3.6GPIO InterfaceFigure 9. SMII Interface Example GPIO Signal Recommendations 3.6.1Signal Interface3.6.2Design Notes 3.7.1Signal Interface I2C Signal Recommendations3.7I2C Interface 3.7.2Device Connection3.8USB Interface Figure 10. I2C EEPROM Interface ExampleProduct Line Network Processor3.8.1Signal Interface USB Host/Device Signal Recommendations3.8.2Device Connection Figure 11. USB Host Down Stream Interface ExampleHost Device3.9UTOPIA Level 2 Interface Figure 12. USB Device Interface ExampleDevice HostUTOPIA Signal Recommendations 3.9.1Signal Interface3.9.2Device Connection 3.10HSS Interface Figure 13. UTOPIA Interface ExampleAnalog Front ATM Layer Device3.10.1Signal Interface High-Speed,Serial InterfaceHigh-Speed,Serial Interface Transmit frame3.10.2Device Connection 3.11SSP InterfaceFigure 14. HSS Interface Example 3.11.1Signal Interface 3.11.2Device ConnectionSynchronous Serial Peripheral Port Interface SPI Flash3.12PCI Interface 3.12.1Signal InterfacePCI Controller Sheet 1 of 3.12.2PCI Interface Block Diagram PCI Controller Sheet 2 of3.12.3Supporting 5 V PCI Interface Figure 16. PCI InterfaceCompact PCI Bus cPCI J13.12.4PCI Option Interface 3.3V LogicPCI Device PCI DevicePage 3.13JTAG Interface 3.12.5Design Notes3.13.1Signal Interface 3.14.1Clock SignalsClock Signals 3.14Input System Clock3.14.3Device Connection 3.15PowerIntel IXP46X 3.15.5Power Sequence 3.15.6Reset TimingPower Interface Sheet 2 of 3.15.1De-CouplingCapacitance RecommendationsFebruary Document Number 305261 RevisionFebruary Document Number 305261 Revision4.4Component Placement 4.0General PCB Guide4.1PCB Overview 4.2General RecommendationsFigure 19. Component Placement on a PCB 4.5Stack-UpSelectionInexpensive Medium FrequencyUncontrolled signal trace impedance Low-impedancepower distributionHigher cost More weight Poor routing densityFigure 20. 8-LayerStackup Figure 21. 6-LayerStackup5.1Overview 5.0General Layout and Routing Guide5.2General Layout Guidelines 5.2.1General Component Spacing Figure 22. Signal Changing Reference PlanesVIAs 25 mils min 25 mils min 25 mils min Figure 24. Poor Design Practice for VIA PlacementFlush Via min Potential Bridge min 5.2.2Clock Signal Considerations PGA or BGA Package5.2.4MII Signal Considerations 5.2.3SMII Signal Considerations5.2.5USB Considerations 5.2.6Cross-Talk 5.2.7EMI-DesignConsiderations5.2.9Power and Ground Plane 5.2.8Trace ImpedanceFebruary Document Number 305261 RevisionFebruary Document Number 305261 Revision6.1Electrical Interface 6.0PCI Interface Design Considerations6.2Topology 6.3Clock Distribution Figure 26. PCI Address/Data TopologyPCI Slot Table 25. PCI Address/Data Routing Guidelines6.3.1Trace Length Limits PCI DevicesClock Driver6.3.2Routing Guidelines 6.3.3Signal LoadingFebruary DDR Signal Groups 7.0DDR-SDRAM7.1Introduction TableFigure 28. Processor-DDRInterface ProcessorsLine of Network DDR SDRAMFebruary Document Number: 305261, Revision:Supported Memory Configurations VTT Signal Termination SignalTermination Intel IXP46X7.1.1Selecting VTT Power Supply Figure 30. VTT Terminating CircuitryIXP46X DDR SDRAMFigure 31. DDR Command and Control Setup and Hold Control/Command ValidDDR M CLK 7.1.2Signal-TimingAnalysisData Figure 32. DDR Data to DQS Read Timing ParametersDDR Data to DQS Read Timing Parameters Figure 33. DDR-Data-to-DQS-WriteTiming Parameters Data ValidDDR Data to DQS Write Timing Parameters Data7.1.3Printed Circuit Board Layer Stackup DDR-Clock-to-DQS-WriteTiming Parameters7.1.4Printed Circuit Board Controlled Impedance Figure 35. Printed Circuit Board Layer StackupFebruary 7.1.5Timing Relationships Figure 31 on page -Table 29 on page—Table 30 on page —Table 31 on page Figure 32 on page -Table 30 on page7.1.7Routing Guidelines 7.1.6Resistive Compensation Register Rcomp7.1.7.1Clock Group 7.1.7.2Data, Command, and Control Groups Clock Signal Group Routing Guidelines7.2Simulation Results 7.2.1Clock GroupFebruary Document Number: 305261, Revision:7.2.2Data Group FebruaryTL1 Tpd = 175 ps/in Figure 39. DDR Data Topology Two-Bankx16 Devices FebruaryFebruary Document Number: 305261, Revision:February February Document Number 305261, Revision7.2.3Control Group February Document Number 305261, Revision7.2.4Command Group TL1 Tpd = 175 ps/inTL2 Tpd = 175 ps/in TL3 Tpd = 175 ps/inFebruary Document Number 305261, RevisionFebruary February Document Number 305261, RevisionFebruary 7.2.5RCVENIN and RCVENOUT Figure 49. DDR RCVENIN/RCVENOUT TopologyFebruary February Document Number 305261, RevisionFebruary Document Number 305261, Revision