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Intel IXP46X, IXP45X manual February

Models: IXP45X IXP46X

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

Figure 50. DDR RCVENIN/RCVENOUT Simulation Results (Rseries = 0 Ω)

The simulation results in Figure 50 are for the RCVENIN/RCVENOUT circuit with a 0-Ωseries resistor, the voltage waveform meets the DDR device input voltage requirements. Vil(max) of Vref – 0.150 or 1.10 V and Vih(min) of Vref + 0.150 or 1.40 V are easily achieved at the receiver (RCVENIN). However, the receiver waveform must also not exceed a maximum voltage of Vin(max) = 2.8 V or the minimum voltage of Vin(min) = -0.3 V and the waveforms at the IXP45X/IXP46X network processors are outside of these limits. A different series resistor should be chosen. The results of using a 60-Ωresistor are shown in Figure 51.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
106	Document Number: 305261, Revision: 004

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Contents

February Hardware Design GuidelinesDocument No 305261 Revision February Contents Introduction6.0 PCI Interface Design Considerations February5.0 General Layout and Routing Guide Document Number 305261, RevisionFigures Tables Revision Revision HistoryDate DescriptionFebruary 1.1Content Overview 1.0Introduction1.2Related Documentation 1.4Overview 1.3Acronyms and AbbreviationsList of Acronyms and Abbreviations 32-bitPCI interface Master/Target 33/66 MHz Cryptography Figure 1. Intel IXP465 Component Block DiagramMII/SMII Unit1.5Typical Applications 2.1System Architecture Description 2.0System Architecture2.2System Memory Map Line of Network JTAGIntelIXP46X Product Processors3.0General Hardware Design Considerations 3.1Soft Fusible FeaturesSignal Type Definitions Table3.2DDR-266SDRAM Interface 3.2.1Signal InterfaceSoft Fusible Features DDR SDRAM Interface Pin Description Sheet 1 ofDDR SDRAM Interface Pin Description Sheet 2 of 3.2.2DDR SDRAM Memory Interface 3.3Expansion Bus3.2.3DDR SDRAM Initialization 3.3.2Reset Configuration Straps 3.3.1Signal InterfaceExpansion Bus Signal Recommendations Name Boot/Reset Strapping Configuration Sheet 1 ofTable Function3.3.38-BitDevice Interface Boot/Reset Strapping Configuration Sheet 2 of3.3.416-BitDevice Interface 3.3.532-BitDevice Interface 32-Bit-WordAccess Byte Access16-Bit-WordAccess 8-BitDevice32-Bit-WordAccess Byte Access16-Bit-WordAccess 8-BitDeviceFigure 5. Flash Interface Example Intel Flash3.3.6Flash Interface 16-Bit-WordAccess3.3.8Design Notes 3.4UART Interface3.3.7SRAM Interface Figure 6. Expansion Bus SRAM Interface3.4.1Signal Interface UART Signal RecommendationsFigure 7. UART Interface Example ConnectorMII/SMII Interface UART InterfaceMII NPE A Signal Recommendations 3.5.1Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 of MII NPE B Signal Recommendations Sheet 2 of MII NPE C Signal RecommendationsFigure 8. MII Interface Example 3.5.2Device Connection, MII10/100 3.5.3Signal Interface, SMII 3.5.4Device Connection, SMII 3.6GPIO InterfaceFigure 9. SMII Interface Example GPIO Signal Recommendations 3.6.1Signal Interface3.6.2Design Notes 3.7I2C Interface 3.7.1Signal InterfaceI2C Signal Recommendations 3.7.2Device ConnectionProduct Line 3.8USB InterfaceFigure 10. I2C EEPROM Interface Example Network Processor3.8.1Signal Interface USB Host/Device Signal RecommendationsHost 3.8.2Device ConnectionFigure 11. USB Host Down Stream Interface Example DeviceDevice 3.9UTOPIA Level 2 InterfaceFigure 12. USB Device Interface Example HostUTOPIA Signal Recommendations 3.9.1Signal Interface3.9.2Device Connection Analog Front 3.10HSS InterfaceFigure 13. UTOPIA Interface Example ATM Layer Device3.10.1Signal Interface High-Speed,Serial InterfaceHigh-Speed,Serial Interface Transmit frame3.10.2Device Connection 3.11SSP InterfaceFigure 14. HSS Interface Example Synchronous Serial Peripheral Port Interface 3.11.1Signal Interface3.11.2Device Connection SPI Flash3.12PCI Interface 3.12.1Signal InterfacePCI Controller Sheet 1 of 3.12.2PCI Interface Block Diagram PCI Controller Sheet 2 ofCompact PCI Bus 3.12.3Supporting 5 V PCI InterfaceFigure 16. PCI Interface cPCI J1PCI Device 3.12.4PCI Option Interface3.3V Logic PCI DevicePage 3.13JTAG Interface 3.12.5Design NotesClock Signals 3.13.1Signal Interface3.14.1Clock Signals 3.14Input System Clock3.14.3Device Connection 3.15PowerIntel IXP46X Power Interface Sheet 2 of 3.15.5Power Sequence3.15.6Reset Timing 3.15.1De-CouplingCapacitance RecommendationsFebruary Document Number 305261 RevisionFebruary Document Number 305261 Revision4.1PCB Overview 4.4Component Placement4.0General PCB Guide 4.2General RecommendationsInexpensive Figure 19. Component Placement on a PCB4.5Stack-UpSelection Medium FrequencyHigher cost More weight Uncontrolled signal trace impedanceLow-impedancepower distribution Poor routing densityFigure 20. 8-LayerStackup Figure 21. 6-LayerStackup5.1Overview 5.0General Layout and Routing Guide5.2General Layout Guidelines 5.2.1General Component Spacing Figure 22. Signal Changing Reference PlanesVIAs 25 mils min 25 mils min 25 mils min Figure 24. Poor Design Practice for VIA PlacementFlush Via min Potential Bridge min 5.2.2Clock Signal Considerations PGA or BGA Package5.2.4MII Signal Considerations 5.2.3SMII Signal Considerations5.2.5USB Considerations 5.2.6Cross-Talk 5.2.7EMI-DesignConsiderationsFebruary 5.2.9Power and Ground Plane5.2.8Trace Impedance Document Number 305261 RevisionFebruary Document Number 305261 Revision6.1Electrical Interface 6.0PCI Interface Design Considerations6.2Topology PCI Slot 6.3Clock DistributionFigure 26. PCI Address/Data Topology Table 25. PCI Address/Data Routing GuidelinesClock 6.3.1Trace Length LimitsPCI Devices Driver6.3.2Routing Guidelines 6.3.3Signal LoadingFebruary 7.1Introduction DDR Signal Groups7.0DDR-SDRAM TableLine of Network Figure 28. Processor-DDRInterfaceProcessors DDR SDRAMFebruary Document Number: 305261, Revision:Supported Memory Configurations Termination VTT Signal TerminationSignal Intel IXP46XIXP46X 7.1.1Selecting VTT Power SupplyFigure 30. VTT Terminating Circuitry DDR SDRAMDDR M CLK Figure 31. DDR Command and Control Setup and HoldControl/Command Valid 7.1.2Signal-TimingAnalysisData Figure 32. DDR Data to DQS Read Timing ParametersDDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters Figure 33. DDR-Data-to-DQS-WriteTiming ParametersData Valid Data7.1.3Printed Circuit Board Layer Stackup DDR-Clock-to-DQS-WriteTiming Parameters7.1.4Printed Circuit Board Controlled Impedance Figure 35. Printed Circuit Board Layer StackupFebruary —Table 30 on page —Table 31 on page 7.1.5Timing RelationshipsFigure 31 on page -Table 29 on page Figure 32 on page -Table 30 on page7.1.7Routing Guidelines 7.1.6Resistive Compensation Register Rcomp7.1.7.1Clock Group 7.1.7.2Data, Command, and Control Groups Clock Signal Group Routing Guidelines7.2Simulation Results 7.2.1Clock GroupFebruary Document Number: 305261, Revision:7.2.2Data Group FebruaryTL1 Tpd = 175 ps/in Figure 39. DDR Data Topology Two-Bankx16 Devices FebruaryFebruary Document Number: 305261, Revision:February February Document Number 305261, Revision7.2.3Control Group February Document Number 305261, RevisionTL2 Tpd = 175 ps/in 7.2.4Command GroupTL1 Tpd = 175 ps/in TL3 Tpd = 175 ps/inFebruary Document Number 305261, RevisionFebruary February Document Number 305261, RevisionFebruary 7.2.5RCVENIN and RCVENOUT Figure 49. DDR RCVENIN/RCVENOUT TopologyFebruary February Document Number 305261, RevisionFebruary Document Number 305261, Revision