Intel IXP45X 7.1.7.2Data, Command, and Control Groups, Clock Signal Group Routing Guidelines

DDR-SDRAM—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Table 34.	Clock Signal Group Routing Guidelines
		Parameter	Definition
	Signal Group Members		DDRI_CK[2:0] and DDRI_CK_N[2:0]
	Topology		Differential Pair Point to Point (1 Driver, 2 Receivers)
	Single Ended Trace Impedance (Zo)		60 Ωs
	Differential Mode Impedance (Zdiff)		120 Ωs
	Nominal Trace Width1		Internal (Strip Line) 3.5 mils, External (Micro Strip) 5 mils
	Nominal Pair Spacing (edge to edge) 2		Internal (Strip Line) 10.5 mils, External (Micro Strip) 10 mils
	Minimum Pair to Pair Spacing		Any layer 20mils
	Minimum Spacing to Other DDR Signals		20.0 mils
	Minimum Spacing to non-DDR Signals		25.0 mils
	Maximum Via Count		4 per trace
			8 per differential pair
	DDRI_CK to DDRI_CK_N Length Matching		Match total length to +/- 10 mils between clocks
	Notes:
	1.	Nominal trace width is determined by board physical characteristics and stack-up. This value should
		be verified with the PWB manufacturer to achieve the desired Zo.
	2.	Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value
		should be verified with the PWB manufacturer to achieve the desired Zdiff.

7.1.7.2Data, Command, and Control Groups

The data, command, and control signal groups include all signals other than the clock group signals. The groups should be routed on internal layers, except for pin escapes. It is recommended that pin escape vias be located directly adjacent to the ball pads on all signals. Surface layer routing should be minimized. The following table provides routing guidelines for signals within these groups.

Table 35. Data, Command, and Control Group Routing Guidelines

	Parameter	Definition
		DDRI_CB[7:0], DDRI_DQ[31:0], DDRI_DQS[4:0], DDRI_DM[4:0],
Signal Group Members		DDRI_CKE[1:0], DDRI_CS_N[1:0], DDRI_MA[13:0],
		DDRI_BA[1:0], DDRI_RAS_N, DDRI_CAS_N, DDRI_WE_N
Topology		Single-Ended, Point-to-Point (1 Driver, 6 Receivers max)
Single Ended Trace Impedance (Zo)		50 Ω
Nominal Trace Width1		Layers 3, 4, 6, 7, 9, and 10: 5.7 mils
Minimum Spacing to DDR Clock Signals		20.0 mils
Minimum Spacing to other DDR Signals		10.0 mils
Minimum Spacing to non-DDR Signals		25.0 mils
Maximum Via Count		6 per signal
Length Matching		See Table 33 on page 87
Notes:
1.	Nominal trace width is determined by board physical characteristics and stack-up. This value should
	be verified with the PWB manufacturer to achieve the desired Zo.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261, Revision: 004	89