Manuals / Intel / Computer Equipment / Computer Hardware

Intel IXP45X, IXP46X manual 3.9UTOPIA Level 2 Interface, USB Device Interface Example, Host

Models: IXP45X IXP46X

1 108

Download 108 pages 42.83 Kb

Page 41

Figure 12. USB Device Interface Example

General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Figure 12. USB Device Interface Example

Device					Host
Intel® IXP46X
Product Line
Network Processor
	USB_3V3	V_BUS	V_BUS
	1.5 KΩ
	Look at
	Note 1&2
USB_DPOS	18 Ω			D
USB_DPOS	FERRITE			D
(D+)	FERRITE			+	HOST
(D+)				+

	22 pF	22 pF		D-
	USB
	Port
USB_DNEG	18 Ω		15 KΩ	15 KΩ
USB_DNEG	18 Ω
(D-)	FERRITE
	22 pF	22 pF
					B4106-003

3.9UTOPIA Level 2 Interface

The IXP45X/IXP46X network processors support the industry-standard UTOPIA Level 2 bus interface. A dedicated Network Processor Engine (NPE) handles segmentation and reassembly of ATM cells, CRC checking/generation, and transfer of data to/from memory. This allows parallel processing of data traffic on the UTOPIA interface, off- loading processor overhead required by the Intel XScale processor.

The UTOPIA module is configured as a master and can support single-PHY (SPHY) or multi-PHY (MPHY).

The IXP45X/IXP46X network processors are in compliance with the ATM Forum, UTOPIA Level 2 Specification, Revision 1.0. For optimal design results, the guidelines of the specification should be followed.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	41

Image 41

Intel IXP45X, IXP46X manual 3.9UTOPIA Level 2 Interface, USB Device Interface Example, Host

Contents

Document No 305261 Revision Hardware Design GuidelinesFebruary February Introduction Contents5.0 General Layout and Routing Guide February6.0 PCI Interface Design Considerations Document Number 305261, RevisionFigures Tables Date Revision HistoryRevision DescriptionFebruary 1.0Introduction 1.1Content Overview1.2Related Documentation List of Acronyms and Abbreviations 1.3Acronyms and Abbreviations1.4Overview 32-bitPCI interface Master/Target 33/66 MHz MII/SMII Figure 1. Intel IXP465 Component Block DiagramCryptography Unit1.5Typical Applications 2.2System Memory Map 2.0System Architecture2.1System Architecture Description IntelIXP46X Product JTAGLine of Network ProcessorsSignal Type Definitions 3.1Soft Fusible Features3.0General Hardware Design Considerations TableSoft Fusible Features 3.2.1Signal Interface3.2DDR-266SDRAM Interface DDR SDRAM Interface Pin Description Sheet 1 ofDDR SDRAM Interface Pin Description Sheet 2 of 3.2.3DDR SDRAM Initialization 3.3Expansion Bus3.2.2DDR SDRAM Memory Interface Expansion Bus Signal Recommendations 3.3.1Signal Interface3.3.2Reset Configuration Straps Table Boot/Reset Strapping Configuration Sheet 1 ofName Function3.3.416-BitDevice Interface Boot/Reset Strapping Configuration Sheet 2 of3.3.38-BitDevice Interface 3.3.532-BitDevice Interface 16-Bit-WordAccess Byte Access32-Bit-WordAccess 8-BitDevice16-Bit-WordAccess Byte Access32-Bit-WordAccess 8-BitDevice3.3.6Flash Interface Intel FlashFigure 5. Flash Interface Example 16-Bit-WordAccess3.3.7SRAM Interface 3.4UART Interface3.3.8Design Notes Figure 6. Expansion Bus SRAM InterfaceUART Signal Recommendations 3.4.1Signal InterfaceMII/SMII Interface ConnectorFigure 7. UART Interface Example UART InterfaceMII NPE B Signal Recommendations Sheet 1 of 3.5.1Signal Interface MIIMII NPE A Signal Recommendations MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2 of10/100 3.5.2Device Connection, MIIFigure 8. MII Interface Example 3.5.3Signal Interface, SMII Figure 9. SMII Interface Example 3.6GPIO Interface3.5.4Device Connection, SMII 3.6.2Design Notes 3.6.1Signal InterfaceGPIO Signal Recommendations I2C Signal Recommendations 3.7.1Signal Interface3.7I2C Interface 3.7.2Device ConnectionFigure 10. I2C EEPROM Interface Example 3.8USB InterfaceProduct Line Network ProcessorUSB Host/Device Signal Recommendations 3.8.1Signal InterfaceFigure 11. USB Host Down Stream Interface Example 3.8.2Device ConnectionHost DeviceFigure 12. USB Device Interface Example 3.9UTOPIA Level 2 InterfaceDevice Host3.9.2Device Connection 3.9.1Signal InterfaceUTOPIA Signal Recommendations Figure 13. UTOPIA Interface Example 3.10HSS InterfaceAnalog Front ATM Layer DeviceHigh-Speed,Serial Interface 3.10.1Signal InterfaceTransmit frame High-Speed,Serial InterfaceFigure 14. HSS Interface Example 3.11SSP Interface3.10.2Device Connection 3.11.2Device Connection 3.11.1Signal InterfaceSynchronous Serial Peripheral Port Interface SPI FlashPCI Controller Sheet 1 of 3.12.1Signal Interface3.12PCI Interface PCI Controller Sheet 2 of 3.12.2PCI Interface Block DiagramFigure 16. PCI Interface 3.12.3Supporting 5 V PCI InterfaceCompact PCI Bus cPCI J13.3V Logic 3.12.4PCI Option InterfacePCI Device PCI DevicePage 3.12.5Design Notes 3.13JTAG Interface3.14.1Clock Signals 3.13.1Signal InterfaceClock Signals 3.14Input System ClockIntel IXP46X 3.15Power3.14.3Device Connection 3.15.6Reset Timing 3.15.5Power SequencePower Interface Sheet 2 of 3.15.1De-CouplingCapacitance RecommendationsDocument Number 305261 Revision FebruaryDocument Number 305261 Revision February4.0General PCB Guide 4.4Component Placement4.1PCB Overview 4.2General Recommendations4.5Stack-UpSelection Figure 19. Component Placement on a PCBInexpensive Medium FrequencyLow-impedancepower distribution Uncontrolled signal trace impedanceHigher cost More weight Poor routing densityFigure 21. 6-LayerStackup Figure 20. 8-LayerStackup5.2General Layout Guidelines 5.0General Layout and Routing Guide5.1Overview VIAs Figure 22. Signal Changing Reference Planes5.2.1General Component Spacing Flush Via min Potential Bridge min Figure 24. Poor Design Practice for VIA Placement25 mils min 25 mils min 25 mils min PGA or BGA Package 5.2.2Clock Signal Considerations5.2.5USB Considerations 5.2.3SMII Signal Considerations5.2.4MII Signal Considerations 5.2.7EMI-DesignConsiderations 5.2.6Cross-Talk5.2.8Trace Impedance 5.2.9Power and Ground PlaneFebruary Document Number 305261 RevisionDocument Number 305261 Revision February6.2Topology 6.0PCI Interface Design Considerations6.1Electrical Interface Figure 26. PCI Address/Data Topology 6.3Clock DistributionPCI Slot Table 25. PCI Address/Data Routing GuidelinesPCI Devices 6.3.1Trace Length LimitsClock DriverFebruary 6.3.3Signal Loading6.3.2Routing Guidelines 7.0DDR-SDRAM DDR Signal Groups7.1Introduction TableProcessors Figure 28. Processor-DDRInterfaceLine of Network DDR SDRAMDocument Number: 305261, Revision: FebruarySupported Memory Configurations Signal VTT Signal TerminationTermination Intel IXP46XFigure 30. VTT Terminating Circuitry 7.1.1Selecting VTT Power SupplyIXP46X DDR SDRAMControl/Command Valid Figure 31. DDR Command and Control Setup and HoldDDR M CLK 7.1.2Signal-TimingAnalysisDDR Data to DQS Read Timing Parameters Figure 32. DDR Data to DQS Read Timing ParametersData Data Valid Figure 33. DDR-Data-to-DQS-WriteTiming ParametersDDR Data to DQS Write Timing Parameters DataDDR-Clock-to-DQS-WriteTiming Parameters 7.1.3Printed Circuit Board Layer StackupFigure 35. Printed Circuit Board Layer Stackup 7.1.4Printed Circuit Board Controlled ImpedanceFebruary Figure 31 on page -Table 29 on page 7.1.5Timing Relationships—Table 30 on page —Table 31 on page Figure 32 on page -Table 30 on page7.1.7.1Clock Group 7.1.6Resistive Compensation Register Rcomp7.1.7Routing Guidelines Clock Signal Group Routing Guidelines 7.1.7.2Data, Command, and Control Groups7.2.1Clock Group 7.2Simulation ResultsDocument Number: 305261, Revision: FebruaryFebruary 7.2.2Data GroupTL1 Tpd = 175 ps/in February Figure 39. DDR Data Topology Two-Bankx16 DevicesDocument Number: 305261, Revision: FebruaryFebruary Document Number 305261, Revision February7.2.3Control Group Document Number 305261, Revision FebruaryTL1 Tpd = 175 ps/in 7.2.4Command GroupTL2 Tpd = 175 ps/in TL3 Tpd = 175 ps/inDocument Number 305261, Revision FebruaryFebruary Document Number 305261, Revision FebruaryFebruary Figure 49. DDR RCVENIN/RCVENOUT Topology 7.2.5RCVENIN and RCVENOUTFebruary Document Number 305261, Revision FebruaryDocument Number 305261, Revision February