Intel IXP45X, IXP46X instruction

General PCB Guide—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

•Poor routing density

•Uncontrolled signal trace impedance

•Lack of power/ground planes, resulting in unacceptable cross-talk

•Relatively high-impedance power distribution circuitry, resulting in noise on the power and ground rails

•High-speed circuits require multi-layer printed circuit boards:

—Advantages:

•Controlled-impedance traces

•Low-impedance power distribution

—Disadvantages:

•Higher cost

•More weight

•Manufactured by fewer vendors

•Symmetry is essential to keep the board stack-up symmetric about the center This minimizes warping

•For best impedance control, have:

—No more than two signal layers between every power/ground plane pair

—No more than one embedded micro-strip layer under the top/bottom layers

•For best noise control, route adjacent layers orthogonally. Avoid layer-to-layer parallelism.

•Fabrication house must agree on design rules, including:

—Trace width, trace separation

—Drill/via sizes

•The distance between the signal layer and ground (or power) should be minimized to reduce the loop area enclosed by the return current

—Use 0.7:1 ratio as a minimum.

For example: 5-mil traces, 7-mil prepreg thickness to adjacent power/ground.

Figure 20 gives an example for a six-layer and eight-layer board. For stripline (signals between planes), the stackup should be such that the signal line is closer to one of the planes by a factor of five or more. Then the trace impedance is controlled predominantly by the distance to the nearest plane.

Figure 20 and Figure 21 illustrate the proposed stackup for the six- and eight-layer boards.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	61

Image 61

Intel IXP45X, IXP46X manual Controlled-impedance traces Low-impedance power distribution

Contents

February Hardware Design Guidelines HDD Contents 12.1 Figures Tables Control Group Topology Transmission Line Characteristics Date Revision Description Revision History HDD Chapter Name Description Content Overview Title Document # Related Documentation List of Acronyms and Abbreviations OverviewTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical Applications System Memory Map System Architecture Description Intel IXP465 Example System Block Diagram Signal Type Definitions Soft Fusible FeaturesSymbol Description Soft Fusible Features Signal InterfaceDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1 Ddriwen DDR Sdram Interface Pin Description Sheet 2Ddrircveninn Ddrircomp DDR Sdram Memory Interface Expansion BusDDR Sdram Initialization Expansion Bus Signal Recommendations Reset Configuration StrapsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 1 3 8-Bit Device Interface Boot/Reset Strapping Configuration Sheet 24 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash Interface Sram Interface Uart InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal Recommendations Uart Interface Example MII/SMII Interface MII NPE a Signal Recommendations Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2 Device Connection, MII MAC Management Signal Recommendations NPE A,B,CNPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, Smii Device Connection, Smii Gpio Interface Gpio Signal Recommendations I2C Interface I2C Signal RecommendationsDevice Connection I2C Eeprom Interface Example USB Interface USB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 Interface Utopia Signal Recommendations Utopia Interface Example HSS Interface HSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0 HSSTXCLK1 HSSTXDATA1HSSRXDATA1 HSSRXCLK1 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface PCI Controller Sheet 1 PCI InterfaceInput Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block Diagram PCI Interface Supporting 5 V PCI Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Option Interface PCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Signals Clock SignalsInput System Clock Clock Oscillator Power Interface Sheet 1 PowerName Nominal Description Voltage Reset Timing Power SequenceDe-Coupling Capacitance Recommendations VCC De-Coupling HDD HDD PCB Overview Component PlacementGeneral Recommendations Component Selection Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations MII Signal Considerations Smii Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-Talk Trace Impedance Power and Ground Plane HDD Topology Electrical Interface@33 MHz @66 MHz PCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading Group Signal Name Description No of Single Ended Signals DDR Signal GroupsIntroduction DDRIDQS40 DDR Sdram HDD Clock Banks Memory Size Supported Memory Configurations VTT VTT Terminating Circuitry Selecting VTT Power Supply Symbol Parameter Min Max Units DDR Command and Control Setup and Hold ValuesDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Clock Group Resistive Compensation Register Rcomp Data, Command, and Control Group Routing Guidelines Clock Signal Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Simulation Results Clock Group Topology Transmission Line CharacteristicsClock Group Transmission Line Length DDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data Group Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line Characteristics DDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command Group DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108