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Intel IXP46X, IXP45X manual 7.2.3Control Group

Models: IXP45X IXP46X

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7.2.3Control Group

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

7.2.3Control Group

The control signal group includes the signals DDRI_CS[1:0] and DDRI_CKE[1:0]. The following simulations were constructed for the 2 bank x16 device configuration where each signal would have three receivers.

Table 38 identifies the transmission line lengths for the chip select (CS0) topology shown in Figure 43 on page 98. These lengths were chosen as realistic goals given the IXP45X/IXP46X network processors to DDR body to body separation of no more than 500 mils.

Table 38. Control Group Topology Transmission Line Characteristics

Transmission Line	Length

TL1 (Tpd = 175 ps/in)	~ 600 mils
TL2 (Tpd = 175 ps/in)	~ 50 mils
TL3 (Tpd = 175 ps/in)	~ 1,100 mils
TL4 (Tpd = 175 ps/in)	~ 50 mils
TL5, TL6, TL7 (Tpd = 175 ps/in)	~ 800 mils
TL8, TL9, TL10 (Tpd = 175 ps/in)	~ 300 mils

Figure 43. DDR Control (CS0) Topology: Two-Bank x16 Devices

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
98	Document Number: 305261, Revision: 004

Image 98

Intel IXP46X, IXP45X manual 7.2.3Control Group

Contents

Document No 305261 Revision Hardware Design GuidelinesFebruary February Contents Introduction6.0 PCI Interface Design Considerations February5.0 General Layout and Routing Guide Document Number 305261, RevisionFigures Tables Revision Revision HistoryDate DescriptionFebruary 1.1Content Overview 1.0Introduction1.2Related Documentation List of Acronyms and Abbreviations 1.3Acronyms and Abbreviations1.4Overview 32-bitPCI interface Master/Target 33/66 MHz Cryptography Figure 1. Intel IXP465 Component Block DiagramMII/SMII Unit1.5Typical Applications 2.2System Memory Map 2.0System Architecture2.1System Architecture Description Line of Network JTAGIntelIXP46X Product Processors3.0General Hardware Design Considerations 3.1Soft Fusible FeaturesSignal Type Definitions Table3.2DDR-266SDRAM Interface 3.2.1Signal InterfaceSoft Fusible Features DDR SDRAM Interface Pin Description Sheet 1 ofDDR SDRAM Interface Pin Description Sheet 2 of 3.2.3DDR SDRAM Initialization 3.3Expansion Bus3.2.2DDR SDRAM Memory Interface Expansion Bus Signal Recommendations 3.3.1Signal Interface3.3.2Reset Configuration Straps Name Boot/Reset Strapping Configuration Sheet 1 ofTable Function3.3.416-BitDevice Interface Boot/Reset Strapping Configuration Sheet 2 of3.3.38-BitDevice Interface 3.3.532-BitDevice Interface 32-Bit-WordAccess Byte Access16-Bit-WordAccess 8-BitDevice32-Bit-WordAccess Byte Access16-Bit-WordAccess 8-BitDeviceFigure 5. Flash Interface Example Intel Flash3.3.6Flash Interface 16-Bit-WordAccess3.3.8Design Notes 3.4UART Interface3.3.7SRAM Interface Figure 6. Expansion Bus SRAM Interface3.4.1Signal Interface UART Signal RecommendationsFigure 7. UART Interface Example ConnectorMII/SMII Interface UART InterfaceMII NPE B Signal Recommendations Sheet 1 of 3.5.1Signal Interface MIIMII NPE A Signal Recommendations MII NPE B Signal Recommendations Sheet 2 of MII NPE C Signal Recommendations10/100 3.5.2Device Connection, MIIFigure 8. MII Interface Example 3.5.3Signal Interface, SMII Figure 9. SMII Interface Example 3.6GPIO Interface3.5.4Device Connection, SMII 3.6.2Design Notes 3.6.1Signal InterfaceGPIO Signal Recommendations 3.7I2C Interface 3.7.1Signal InterfaceI2C Signal Recommendations 3.7.2Device ConnectionProduct Line 3.8USB InterfaceFigure 10. I2C EEPROM Interface Example Network Processor3.8.1Signal Interface USB Host/Device Signal RecommendationsHost 3.8.2Device ConnectionFigure 11. USB Host Down Stream Interface Example DeviceDevice 3.9UTOPIA Level 2 InterfaceFigure 12. USB Device Interface Example Host3.9.2Device Connection 3.9.1Signal InterfaceUTOPIA Signal Recommendations Analog Front 3.10HSS InterfaceFigure 13. UTOPIA Interface Example ATM Layer Device3.10.1Signal Interface High-Speed,Serial InterfaceHigh-Speed,Serial Interface Transmit frameFigure 14. HSS Interface Example 3.11SSP Interface3.10.2Device Connection Synchronous Serial Peripheral Port Interface 3.11.1Signal Interface3.11.2Device Connection SPI FlashPCI Controller Sheet 1 of 3.12.1Signal Interface3.12PCI Interface 3.12.2PCI Interface Block Diagram PCI Controller Sheet 2 ofCompact PCI Bus 3.12.3Supporting 5 V PCI InterfaceFigure 16. PCI Interface cPCI J1PCI Device 3.12.4PCI Option Interface3.3V Logic PCI DevicePage 3.13JTAG Interface 3.12.5Design NotesClock Signals 3.13.1Signal Interface3.14.1Clock Signals 3.14Input System ClockIntel IXP46X 3.15Power3.14.3Device Connection Power Interface Sheet 2 of 3.15.5Power Sequence3.15.6Reset Timing 3.15.1De-CouplingCapacitance RecommendationsFebruary Document Number 305261 RevisionFebruary Document Number 305261 Revision4.1PCB Overview 4.4Component Placement4.0General PCB Guide 4.2General RecommendationsInexpensive Figure 19. Component Placement on a PCB4.5Stack-UpSelection Medium FrequencyHigher cost More weight Uncontrolled signal trace impedanceLow-impedancepower distribution Poor routing densityFigure 20. 8-LayerStackup Figure 21. 6-LayerStackup5.2General Layout Guidelines 5.0General Layout and Routing Guide5.1Overview VIAs Figure 22. Signal Changing Reference Planes5.2.1General Component Spacing Flush Via min Potential Bridge min Figure 24. Poor Design Practice for VIA Placement25 mils min 25 mils min 25 mils min 5.2.2Clock Signal Considerations PGA or BGA Package5.2.5USB Considerations 5.2.3SMII Signal Considerations5.2.4MII Signal Considerations 5.2.6Cross-Talk 5.2.7EMI-DesignConsiderationsFebruary 5.2.9Power and Ground Plane5.2.8Trace Impedance Document Number 305261 RevisionFebruary Document Number 305261 Revision6.2Topology 6.0PCI Interface Design Considerations6.1Electrical Interface PCI Slot 6.3Clock DistributionFigure 26. PCI Address/Data Topology Table 25. PCI Address/Data Routing GuidelinesClock 6.3.1Trace Length LimitsPCI Devices DriverFebruary 6.3.3Signal Loading6.3.2Routing Guidelines 7.1Introduction DDR Signal Groups7.0DDR-SDRAM TableLine of Network Figure 28. Processor-DDRInterfaceProcessors DDR SDRAMFebruary Document Number: 305261, Revision:Supported Memory Configurations Termination VTT Signal TerminationSignal Intel IXP46XIXP46X 7.1.1Selecting VTT Power SupplyFigure 30. VTT Terminating Circuitry DDR SDRAMDDR M CLK Figure 31. DDR Command and Control Setup and HoldControl/Command Valid 7.1.2Signal-TimingAnalysisDDR Data to DQS Read Timing Parameters Figure 32. DDR Data to DQS Read Timing ParametersData DDR Data to DQS Write Timing Parameters Figure 33. DDR-Data-to-DQS-WriteTiming ParametersData Valid Data7.1.3Printed Circuit Board Layer Stackup DDR-Clock-to-DQS-WriteTiming Parameters7.1.4Printed Circuit Board Controlled Impedance Figure 35. Printed Circuit Board Layer StackupFebruary —Table 30 on page —Table 31 on page 7.1.5Timing RelationshipsFigure 31 on page -Table 29 on page Figure 32 on page -Table 30 on page7.1.7.1Clock Group 7.1.6Resistive Compensation Register Rcomp7.1.7Routing Guidelines 7.1.7.2Data, Command, and Control Groups Clock Signal Group Routing Guidelines7.2Simulation Results 7.2.1Clock GroupFebruary Document Number: 305261, Revision:7.2.2Data Group FebruaryTL1 Tpd = 175 ps/in Figure 39. DDR Data Topology Two-Bankx16 Devices FebruaryFebruary Document Number: 305261, Revision:February February Document Number 305261, Revision7.2.3Control Group February Document Number 305261, RevisionTL2 Tpd = 175 ps/in 7.2.4Command GroupTL1 Tpd = 175 ps/in TL3 Tpd = 175 ps/inFebruary Document Number 305261, RevisionFebruary February Document Number 305261, RevisionFebruary 7.2.5RCVENIN and RCVENOUT Figure 49. DDR RCVENIN/RCVENOUT TopologyFebruary February Document Number 305261, RevisionFebruary Document Number 305261, Revision