Clock Distribution, Parameter Routing Guidelines | Intel IXP46X

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—PCI Interface Design Considerations

Figure 26. PCI Address/Data Topology

Intel® IXP46X	PCI Slot	PCI Slot	PCI Slot	PCI Slot
Product Line	PCI Slot	PCI Slot	PCI Slot	PCI Slot
Network Processor
A		B	B	B
				B5196 -01

Table 25. PCI Address/Data Routing Guidelines

Parameter	Routing Guidelines

Signal Group	PCI Address/Data

Topology	Daisy Chain

Reference Plane	Ground

Characteristic Trace Impedance	55 Ω ±10%

Nominal Trace Width	5 mils

Nominal Trace Separation	10 mils

Spacing to Other Groups	20 mils

Limit the number of VIAS to 10 per Signal	10

6.3Clock Distribution

In order to meet timing and avoid clock overloading, it is recommended to use point- to-point clock distribution as shown in Figure 27.

Clock skew between interfacing devices is very critical and must be met. The maximum skew must be measured between any two components. If designing a motherboard, the skew must be measured to the expansion card device and not to the PCI connector. Ensure that clock skew between all devices does not exceed the values in Section 6.2.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
72	Document Number: 305261, Revision: 004

Image 72

Intel IXP46X, IXP45X manual Clock Distribution, PCI Address/Data Routing Guidelines, Parameter Routing Guidelines

Contents

Hardware Design Guidelines February HDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics Tables Revision History Date Revision Description HDD Content Overview Chapter Name Description Related Documentation Title Document # Overview List of Acronyms and AbbreviationsTerm Explanation Smii Intel IXP465 Component Block Diagram Typical Applications Dslam System Architecture Description System Memory Map Intel IXP465 Example System Block Diagram Soft Fusible Features Signal Type DefinitionsSymbol Description Signal Interface Soft Fusible FeaturesDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1 DDR Sdram Interface Pin Description Sheet 2 DdriwenDdrircveninn Ddrircomp Expansion Bus DDR Sdram Memory InterfaceDDR Sdram Initialization Reset Configuration Straps Expansion Bus Signal RecommendationsInput Pull Name Recommendations Output Down Boot/Reset Strapping Configuration Sheet 1 Name Function Description Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface4 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface Example Uart Interface Sram InterfaceDesign Notes Uart Signal Recommendations Name Input Pull Recommendations Output Down MII/SMII Interface Uart Interface Example Signal Interface MII MII NPE a Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal Recommendations MAC Management Signal Recommendations NPE A,B,C Device Connection, MIINPE A,B,C Signal Interface, Smii Smii Signal Recommendations NPE A, B, C Gpio Interface Device Connection, Smii Gpio Signal Recommendations I2C Signal Recommendations I2C InterfaceDevice Connection USB Interface I2C Eeprom Interface Example USB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface Example Utopia Signal Recommendations HSS Interface Utopia Interface Example High-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0 HSSTXDATA1 HSSTXCLK1HSSRXDATA1 HSSRXCLK1 SSP Interface HSS Interface Example Synchronous Serial Peripheral Port Interface PCI Interface PCI Controller Sheet 1Input Pull Name Outpu Recommendations Down PCI Interface Block Diagram PCI Controller Sheet 2 Supporting 5 V PCI Interface PCI Interface PCI Option Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3 Clock Signals Clock SignalsInput System Clock Clock Oscillator Power Power Interface Sheet 1Name Nominal Description Voltage Power Sequence Reset TimingDe-Coupling Capacitance Recommendations VCC De-Coupling HDD HDD Component Placement PCB OverviewGeneral Recommendations Component Selection Component Placement on a PCB Stack-Up Selection Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout Guidelines Signal Changing Reference Planes General Component Spacing Good Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGA Smii Signal Considerations MII Signal ConsiderationsUSB Considerations Cross-Talk EMI-Design Considerations Power and Ground Plane Trace Impedance HDD Electrical Interface Topology@33 MHz @66 MHz Clock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines Trace Length Limits PCI Clock Routing Guidelines Signal Loading Routing Guidelines DDR Signal Groups Group Signal Name Description No of Single Ended SignalsIntroduction DDRIDQS40 DDR Sdram HDD Supported Memory Configurations Clock Banks Memory Size VTT Selecting VTT Power Supply VTT Terminating Circuitry DDR Command and Control Setup and Hold Values Symbol Parameter Min Max UnitsDdrmclk DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Signal Group Absolute Minimum Absolute Maximum Length Timing RelationshipsTiming Relationships Resistive Compensation Register Rcomp Clock Group Clock Signal Group Routing Guidelines Data, Command, and Control Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Group Topology Transmission Line Characteristics Simulation ResultsClock Group Transmission Line Length DDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 Devices Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control Group DDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line Characteristics DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Topology DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108