Intel IXP45X, IXP46X manual DDR-Data-to-DQS-WriteTiming Parameters, Data Valid, Ddr M Clk

DDR-SDRAM—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Figure 33. DDR-Data-to-DQS-Write Timing Parameters

T1	T2
T3	T4
T5	T6
DQS
Data
Data Valid
	B3990-001

Table 31.	DDR Data to DQS Write Timing Parameters
	Symbol		Parameter	Min	Max	Units	Notes
	T1		IXP45X/IXP46X network processors output valid for data	1.0		ns	1
			group signals prior to the transition of DQS
	T2		IXP45X/IXP46X network processors output hold time for	1.0		ns	1
			data group signals after the transition of DQS
	T3		Required data group input setup time at DDR memory	0.5		ns	1
			device
	T4		Required data group input hold time at DDR memory	0.5		ns	1
			device
			Allowable setup time difference between IXP45X/IXP46X
	T5		network processors data group output and setup time		0.5	ns	1
			required by DDR memory device
	T6		Allowable hold time difference between IXP45X/IXP46X
			network processors data group output and hold time		0.5	ns	1
			required by DDR memory device
	Notes:
	1.	Data group signals consist of DDRI_DM[4:0], DDRI_DQ[31:0], and DDRI_CB[7:0]

Figure 34. DDR-Clock-to-DQS-Write Timing Parameters

T3	T4
T1	T2
T5	T6
DDR_M_CLK
DQS
	B3991-001

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261, Revision: 004	83