PCI Option Interface | Intel IXP45X, IXP46X instruction

General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Figure 17. PCI 3.3 V to 5 V Logic Translation Interface

Intel® IXP46X	3.3V LOGIC		3.3V Logic
Product Line	3.3V LOGIC	PCI Device_ 1
Product Line		PCI Device_ 1
Network Processor
	3.3V LOGIC		3.3V Logic
	3.3V LOGIC	PCI Device_2
		PCI Device_2
	3.3V LOGIC		3.3V Logic
	3.3V LOGIC	PCI Device_3
	32-Bit BUS	PCI Device_3
	32-Bit BUS
				5.0V
	1K	74CBT3384A
		OE	VCC	4.3V
PCI		10-BIT
Interface			GND	5.0V LOGIC	5.0V Logic
Interface	3.3V LOGIC				5.0V Logic
	3.3V LOGIC		VCC		PCI Device_4
			VCC
	1K	10-BIT		2.87K
	1K
		OE	GND
		74CBT3384A
					B5197 -01

3.12.4PCI Option Interface

The IXP45X/IXP46X network processors can be used in a design as a host or as an option device. This section describes how the IXP45X/IXP46X network processors can be connected as an option device to obtain proper functionality. There are slight differences in the hardware interface when designing for option mode. All routing and board recommendations described in previous sections of this document apply, however the design must use the device pin connections listed in Table 21.

Table 21. PCI Host/Option Interface Pin Description (Sheet 1 of 3)

		Host		Option
	Name	Input	Device-Pin Connection	Input	Description
	Name	Outpu	Device-Pin Connection	Outpu	Description
		Outpu		Outpu
		t		t

	PCI_AD[31:0]	I/O	All address/data signals need to be	I/O	PCI Address/Data bus
	PCI_AD[31:0]	I/O	connected between the two devices.	I/O	PCI Address/Data bus
			connected between the two devices.

	PCI_CBE_N[3:0]	I/O	Connect signals to same pins between	I/O	PCI Command/Byte Enables
	PCI_CBE_N[3:0]	I/O	the two devices.	I/O	PCI Command/Byte Enables
			the two devices.

	PCI_PAR	I/O	Connect signal to same pin between	I/O	PCI Parity
	PCI_PAR	I/O	the two devices.	I/O	PCI Parity
			the two devices.

			Connect signal to same pin between
	PCI_FRAME_N	I/O	the two devices.	I/O	PCI Cycle Frame
			Connect a 10-KΩpull-up resistor.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	51

Image 51

Intel IXP45X, IXP46X manual PCI Option Interface, PCI Host/Option Interface Pin Description Sheet 1

Contents

February Hardware Design Guidelines HDD Contents 12.1 Figures Tables Control Group Topology Transmission Line Characteristics Date Revision Description Revision History HDD Chapter Name Description Content Overview Title Document # Related Documentation Overview List of Acronyms and AbbreviationsTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical Applications System Memory Map System Architecture Description Intel IXP465 Example System Block Diagram Soft Fusible Features Signal Type DefinitionsSymbol Description DDR Sdram Interface Pin Description Sheet 1 Signal InterfaceSoft Fusible Features DDR-266 Sdram Interface Ddrircomp DDR Sdram Interface Pin Description Sheet 2Ddriwen Ddrircveninn Expansion Bus DDR Sdram Memory InterfaceDDR Sdram Initialization Reset Configuration Straps Expansion Bus Signal RecommendationsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 1 Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface4 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash Interface Uart Interface Sram InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal Recommendations Uart Interface Example MII/SMII Interface Signal Interface MII MII NPE a Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE A,B,C Device Connection, MIINPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, Smii Device Connection, Smii Gpio Interface Gpio Signal Recommendations I2C Signal Recommendations I2C InterfaceDevice Connection I2C Eeprom Interface Example USB Interface USB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 Interface Utopia Signal Recommendations Utopia Interface Example HSS Interface HSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0 HSSRXCLK1 HSSTXDATA1HSSTXCLK1 HSSRXDATA1 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface PCI Interface PCI Controller Sheet 1Input Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block Diagram PCI Interface Supporting 5 V PCI Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Option Interface PCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Oscillator Clock SignalsClock Signals Input System Clock Power Power Interface Sheet 1Name Nominal Description Voltage VCC De-Coupling Power SequenceReset Timing De-Coupling Capacitance Recommendations HDD HDD Component Selection Component PlacementPCB Overview General Recommendations Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations Smii Signal Considerations MII Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-Talk Trace Impedance Power and Ground Plane HDD @66 MHz Electrical InterfaceTopology @33 MHz Clock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading DDRIDQS40 DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals Introduction DDR Sdram HDD Clock Banks Memory Size Supported Memory Configurations VTT VTT Terminating Circuitry Selecting VTT Power Supply DDR Command and Control Setup and Hold Values Symbol Parameter Min Max UnitsDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Controlled Impedance Signal Group Absolute Minimum Absolute Maximum Length Timing RelationshipsTiming Relationships Clock Group Resistive Compensation Register Rcomp DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines Parameter Definition Transmission Line Length Clock Group Topology Transmission Line CharacteristicsSimulation Results Clock Group DDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data Group Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line Characteristics DDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command Group DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108