Intel IXP46X, IXP45X manual 3.5.3Signal Interface, SMII

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware Design Considerations

3.5.3Signal Interface, SMII

Serial Media Independent Interface (SMII) is a hardware feature to convey complete MII interface between a MAC and 10/100 PHY interface with two data pins per port and one synchronizing signal for multi PHYs.

Table 12. SMII Signal Recommendations: NPE A, B, C

		Input/	Pull
	Name		Up/	Recommendations
		Output
			Down
SMII_TXDATA[4]		O	No	NPE A
				Transmit Data Port 4.
				NPE A
SMII_RXDATA[4]		I	Yes	Received Data Port 4.
				When this interface/signal is enabled and is not being used in a system design, the
				interface/signal should be pulled high with a 10-KΩresistor.
				NPE A,B,C
SMII_CLK		I	Yes	Reference Clock, 125-MHz.
				When this interface/signal is enabled and is not being used in a system design, the
				interface/signal should be pulled high with a 10-KΩresistor.
SMII_TXDATA[0] /				NPE B
SMII_TXDATA[1] /		O	No
SMII_TXDATA[2] /				Transmit Data Ports 3,2,1,0.
SMII_TXDATA[3]
				NPE B
				Transmit Data Ports 3,2,1,0.
SMII_RXDATA[0] /				When this interface/signal is enabled and is not being used in a system design, the
SMII_RXDATA[1] /		I	Yes	interface/signal should be pulled high with a 10-KΩresistor.
SMII_RXDATA[2] /				One special configuration exists for the board designer. When NPE B is configured in SMII
SMII_RXDATA[3]
				mode of operation and a subset of the four SMII ports are utilized (i.e. All four are enabled
				but only two are being connected). The unused inputs must be tied high with a 10-KΩ
				resistor.
SMII_SYNC		O	No	NPE B
				Synchronous pulse.
				NPE A,B,C
				Management data output.
ETH_MDIO		I/O	Yes	An external pull-up resistor of 1.5 KΩ is required on ETH_MDIO to properly quantify the
				external PHYs used in the system. For specific implementation, see the IEEE 802.3
				specification.
				Should be pulled high through a 10-KΩresistor when not being utilized in the system.
ETH_MDC		I/O	No	NPE A,B,C
				Management data clock.
SMII_TXDATA[5]		O	No	NPE C
				Transmit Data Ports 5.
				NPE C
SMII_RXDATA[5]		I	Yes	Receive Data Ports 5.
				Should be pulled high through a 10-KΩresistor when not being utilized in the system.
Notes:
1.	Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after
	being disabled without asserting a system reset.
2.	Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left
	unconnected.
3.	Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in Note 1 — only require
	pull-ups or pull-downs in the clock-input signals.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
34	Document Number: 305261; Revision: 004