Utopia Signal Recommendations | Intel IXP46X, IXP45X specification

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware Design Considerations

3.9.1Signal Interface

Table 16.		UTOPIA Signal Recommendations

			Input/	Pull
	Name		Input/	Up/	Recommendations
			Output	Down

					UTOPIA Transmit clock input. Also known as UTP_TX_CLK.
UTP_OP_CLK			I	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

					UTOPIA flow control output signal. Also known as the TXENB_N signal.
UTP_OP_FCO			O	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

					Start of Cell. Also known as TX_SOC.
UTP_OP_SOC			O	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled low with a 10-KΩresistor.

UTP_OP_DATA[7:0]			O	No	UTOPIA output data.

					Transmit PHY address bus.
UTP_OP_ADDR[4:0]			I/O	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

					UTOPIA Output data flow control input: Also known as the TXFULL/CLAV signal.
UTP_OP_FCI			I	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

					UTOPIA Receive clock input. Also known as UTP_RX_CLK.
UTP_IP_CLK			I	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

					UTOPIA Input Data flow control input signal. Also known as RXEMPTY/CLAV.
UTP_IP_FCI			I	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

					Start of Cell. Also known as RX_SOC
UTP_IP_SOC			I	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

					UTOPIA input data. Also known as RX_DATA.
UTP_IP_DATA[7:0]			I	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

UTP_IP_ADDR[4:0]			I/O	No	Receive PHY address bus.

					UTOPIA Input Data Flow Control Output signal: Also known as the RX_ENB_N.
UTP_IP_FCO			O	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

Notes:
1.	Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after
	being disabled without asserting a system reset.
2.	Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left
	unconnected.
3.	Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in Note 1 — only require
	pull-ups or pull-downs in the clock-input signals.

3.9.2Device Connection

The following example shown in Figure 13 shows a typical interface to an ADSL Framer via the UTOPIA bus. Notice that depending on the framer used some control signals might be required which can be derived from the Expansion bus or the GPIO signals.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
42	Document Number: 305261; Revision: 004

Image 42

Intel IXP46X, IXP45X manual Utopia Signal Recommendations

Contents

Hardware Design Guidelines February HDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics Tables Revision History Date Revision Description HDD Content Overview Chapter Name Description Related Documentation Title Document # Overview List of Acronyms and AbbreviationsTerm Explanation Smii Intel IXP465 Component Block Diagram Typical Applications Dslam System Architecture Description System Memory Map Intel IXP465 Example System Block Diagram Soft Fusible Features Signal Type DefinitionsSymbol Description DDR-266 Sdram Interface Signal InterfaceSoft Fusible Features DDR Sdram Interface Pin Description Sheet 1 Ddrircveninn DDR Sdram Interface Pin Description Sheet 2Ddriwen Ddrircomp Expansion Bus DDR Sdram Memory InterfaceDDR Sdram Initialization Reset Configuration Straps Expansion Bus Signal RecommendationsInput Pull Name Recommendations Output Down Boot/Reset Strapping Configuration Sheet 1 Name Function Description Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface4 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface Example Uart Interface Sram InterfaceDesign Notes Uart Signal Recommendations Name Input Pull Recommendations Output Down MII/SMII Interface Uart Interface Example Signal Interface MII MII NPE a Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal Recommendations MAC Management Signal Recommendations NPE A,B,C Device Connection, MIINPE A,B,C Signal Interface, Smii Smii Signal Recommendations NPE A, B, C Gpio Interface Device Connection, Smii Gpio Signal Recommendations I2C Signal Recommendations I2C InterfaceDevice Connection USB Interface I2C Eeprom Interface Example USB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface Example Utopia Signal Recommendations HSS Interface Utopia Interface Example HSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0 HSSRXDATA1 HSSTXDATA1HSSTXCLK1 HSSRXCLK1 SSP Interface HSS Interface Example Synchronous Serial Peripheral Port Interface PCI Interface PCI Controller Sheet 1Input Pull Name Outpu Recommendations Down PCI Interface Block Diagram PCI Controller Sheet 2 Supporting 5 V PCI Interface PCI Interface PCI Option Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3 Input System Clock Clock SignalsClock Signals Clock Oscillator Power Power Interface Sheet 1Name Nominal Description Voltage De-Coupling Capacitance Recommendations Power SequenceReset Timing VCC De-Coupling HDD HDD General Recommendations Component PlacementPCB Overview Component Selection Component Placement on a PCB Stack-Up Selection Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout Guidelines Signal Changing Reference Planes General Component Spacing Good Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGA Smii Signal Considerations MII Signal ConsiderationsUSB Considerations Cross-Talk EMI-Design Considerations Power and Ground Plane Trace Impedance HDD @33 MHz Electrical InterfaceTopology @66 MHz Clock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines Trace Length Limits PCI Clock Routing Guidelines Signal Loading Routing Guidelines Introduction DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals DDRIDQS40 DDR Sdram HDD Supported Memory Configurations Clock Banks Memory Size VTT Selecting VTT Power Supply VTT Terminating Circuitry DDR Command and Control Setup and Hold Values Symbol Parameter Min Max UnitsDdrmclk DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Signal Group Absolute Minimum Absolute Maximum Length Timing RelationshipsTiming Relationships Resistive Compensation Register Rcomp Clock Group Parameter Definition Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Group Clock Group Topology Transmission Line CharacteristicsSimulation Results Transmission Line Length DDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 Devices Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control Group DDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line Characteristics DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Topology DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108