Intel IXP46X, IXP45X manual 6.3.2Routing Guidelines, 6.3.3Signal Loading, February

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—PCI Interface Design Considerations

The limitations of the maximum trace length can be calculated with the equations shown in Section 6.2. Solve for TPROP and use it to calculate the maximum trace length. This is a straight-forward calculation, but very critical to meet timing. It is recommended to keep the trace lengths as short as possible and not to exceed TPROP.

Note: For acceptable signal integrity at up to 66 MHz, it is very important to design the PCB board with controller impedance in the range of 55 Ω ±10%.

6.3.2Routing Guidelines

It is recommended to route signals with respect to an adjacent ground plane. If routing signals over power planes, ensure that the signals are referenced to a single power plane voltage level and not multiple levels. For example, you can route signals over a

3.3V plane or a 5 V plane, but do not route the same signal over both planes. If signals are routed over split planes, you must connect the splitting planes with 0.01 µF, high- speed capacitors near the signal crossing the split. The capacitors should be placed no more than 0.25 inches from the point at which the signals cross the split.

This manual does not repeat all the guidelines that are already stated in the PCI Local Bus Specification, Rev. 2.2, instead you should refer to the specification when designing either a motherboard or an expansion card.

6.3.3Signal Loading

Shared PCI signals must be limited to one load on each of the PCI slots. Any violation of expansion board or add-on device trace length or loading limits compromises system- signal integrity.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
74	Document Number: 305261, Revision: 004