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Intel IXP45X, IXP46X manual 3.7I2C Interface, 3.7.1Signal Interface, 3.7.2Device Connection

Models: IXP45X IXP46X

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General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

3.7I2C Interface

The IXP45X/IXP46X network processors support I2C interface and protocol. The hardware-embedded block supports transfer rates in Standard-mode at up to 100 Kbps or Fast-mode at up to 400 Kbps, 7-bit addressing, and Master or Slave mode.

Note: The I2C block does not support 10-bit addressing mode.

Figure 10 shows the schematic for connecting the I2C interface to a 256-byte I2C EEPROM, 7-bit addressing mode (Philips* PC8582C-2T/03).

3.7.1Signal Interface

Table 14.	I2C Signal Recommendations

	Name	Input	Pull
		Input	Up	Recommendations
		Output	Up	Recommendations
		Output	Down

	I2C_SCL	I/O	Yes	Serial Data.
	I2C_SCL	I/O	Yes	Use a 4.7-KΩpull-up resistor.
				Use a 4.7-KΩpull-up resistor.

	I2C_SDA	I/O	Yes	Serial Clock.
	I2C_SDA	I/O	Yes	Use a 4.7-KΩpull-up resistor.
				Use a 4.7-KΩpull-up resistor.

3.7.2Device Connection

More information is available from the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet and the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual.

Note: Because of the characteristics of the I2C bus (Open Drain/Collector) pull-up resistors are required. Use 2 KΩ to 10 KΩ. resistors.

The I2C-Bus Specification, available from Philips Semiconductors*, states:

The external pull-up resistor connected to the bus lines must be adapted to accommodate the shorter maximum permissible rise time for the Fast-mode I2C-bus. For bus loads up to 200 pF, the pull-up device for each bus line can be a resistor; for bus loads between 200 pF and 400 pF, the pull-up device can be a current source (3 mA max.) or a switched resistor circuit. The actual value of the pull-up is system dependent and a guide is presented in the I2C-Bus Specification on determining the maximum and minimum resistors to use when the system is intended for standard or fast-mode I2C bus devices.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	37

Image 37

Intel IXP45X, IXP46X manual 3.7I2C Interface, 3.7.1Signal Interface, 3.7.2Device Connection, I2C Signal Recommendations

Contents

February Hardware Design GuidelinesDocument No 305261 Revision February Introduction Contents5.0 General Layout and Routing Guide February6.0 PCI Interface Design Considerations Document Number 305261, RevisionFigures Tables Date Revision HistoryRevision DescriptionFebruary 1.0Introduction 1.1Content Overview1.2Related Documentation 1.4Overview 1.3Acronyms and AbbreviationsList of Acronyms and Abbreviations 32-bitPCI interface Master/Target 33/66 MHz MII/SMII Figure 1. Intel IXP465 Component Block DiagramCryptography Unit1.5Typical Applications 2.1System Architecture Description 2.0System Architecture2.2System Memory Map IntelIXP46X Product JTAGLine of Network ProcessorsSignal Type Definitions 3.1Soft Fusible Features3.0General Hardware Design Considerations TableSoft Fusible Features 3.2.1Signal Interface3.2DDR-266SDRAM Interface DDR SDRAM Interface Pin Description Sheet 1 ofDDR SDRAM Interface Pin Description Sheet 2 of 3.2.2DDR SDRAM Memory Interface 3.3Expansion Bus3.2.3DDR SDRAM Initialization 3.3.2Reset Configuration Straps 3.3.1Signal InterfaceExpansion Bus Signal Recommendations Table Boot/Reset Strapping Configuration Sheet 1 ofName Function3.3.38-BitDevice Interface Boot/Reset Strapping Configuration Sheet 2 of3.3.416-BitDevice Interface 3.3.532-BitDevice Interface 16-Bit-WordAccess Byte Access32-Bit-WordAccess 8-BitDevice16-Bit-WordAccess Byte Access32-Bit-WordAccess 8-BitDevice3.3.6Flash Interface Intel FlashFigure 5. Flash Interface Example 16-Bit-WordAccess3.3.7SRAM Interface 3.4UART Interface3.3.8Design Notes Figure 6. Expansion Bus SRAM InterfaceUART Signal Recommendations 3.4.1Signal InterfaceMII/SMII Interface ConnectorFigure 7. UART Interface Example UART InterfaceMII NPE A Signal Recommendations 3.5.1Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 of MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2 ofFigure 8. MII Interface Example 3.5.2Device Connection, MII10/100 3.5.3Signal Interface, SMII 3.5.4Device Connection, SMII 3.6GPIO InterfaceFigure 9. SMII Interface Example GPIO Signal Recommendations 3.6.1Signal Interface3.6.2Design Notes I2C Signal Recommendations 3.7.1Signal Interface3.7I2C Interface 3.7.2Device ConnectionFigure 10. I2C EEPROM Interface Example 3.8USB InterfaceProduct Line Network ProcessorUSB Host/Device Signal Recommendations 3.8.1Signal InterfaceFigure 11. USB Host Down Stream Interface Example 3.8.2Device ConnectionHost DeviceFigure 12. USB Device Interface Example 3.9UTOPIA Level 2 InterfaceDevice HostUTOPIA Signal Recommendations 3.9.1Signal Interface3.9.2Device Connection Figure 13. UTOPIA Interface Example 3.10HSS InterfaceAnalog Front ATM Layer DeviceHigh-Speed,Serial Interface 3.10.1Signal InterfaceTransmit frame High-Speed,Serial Interface3.10.2Device Connection 3.11SSP InterfaceFigure 14. HSS Interface Example 3.11.2Device Connection 3.11.1Signal InterfaceSynchronous Serial Peripheral Port Interface SPI Flash3.12PCI Interface 3.12.1Signal InterfacePCI Controller Sheet 1 of PCI Controller Sheet 2 of 3.12.2PCI Interface Block DiagramFigure 16. PCI Interface 3.12.3Supporting 5 V PCI InterfaceCompact PCI Bus cPCI J13.3V Logic 3.12.4PCI Option InterfacePCI Device PCI DevicePage 3.12.5Design Notes 3.13JTAG Interface3.14.1Clock Signals 3.13.1Signal InterfaceClock Signals 3.14Input System Clock3.14.3Device Connection 3.15PowerIntel IXP46X 3.15.6Reset Timing 3.15.5Power SequencePower Interface Sheet 2 of 3.15.1De-CouplingCapacitance RecommendationsDocument Number 305261 Revision FebruaryDocument Number 305261 Revision February4.0General PCB Guide 4.4Component Placement4.1PCB Overview 4.2General Recommendations4.5Stack-UpSelection Figure 19. Component Placement on a PCBInexpensive Medium FrequencyLow-impedancepower distribution Uncontrolled signal trace impedanceHigher cost More weight Poor routing densityFigure 21. 6-LayerStackup Figure 20. 8-LayerStackup5.1Overview 5.0General Layout and Routing Guide5.2General Layout Guidelines 5.2.1General Component Spacing Figure 22. Signal Changing Reference PlanesVIAs 25 mils min 25 mils min 25 mils min Figure 24. Poor Design Practice for VIA PlacementFlush Via min Potential Bridge min PGA or BGA Package 5.2.2Clock Signal Considerations5.2.4MII Signal Considerations 5.2.3SMII Signal Considerations5.2.5USB Considerations 5.2.7EMI-DesignConsiderations 5.2.6Cross-Talk5.2.8Trace Impedance 5.2.9Power and Ground PlaneFebruary Document Number 305261 RevisionDocument Number 305261 Revision February6.1Electrical Interface 6.0PCI Interface Design Considerations6.2Topology Figure 26. PCI Address/Data Topology 6.3Clock DistributionPCI Slot Table 25. PCI Address/Data Routing GuidelinesPCI Devices 6.3.1Trace Length LimitsClock Driver6.3.2Routing Guidelines 6.3.3Signal LoadingFebruary 7.0DDR-SDRAM DDR Signal Groups7.1Introduction TableProcessors Figure 28. Processor-DDRInterfaceLine of Network DDR SDRAMDocument Number: 305261, Revision: FebruarySupported Memory Configurations Signal VTT Signal TerminationTermination Intel IXP46XFigure 30. VTT Terminating Circuitry 7.1.1Selecting VTT Power SupplyIXP46X DDR SDRAMControl/Command Valid Figure 31. DDR Command and Control Setup and HoldDDR M CLK 7.1.2Signal-TimingAnalysisData Figure 32. DDR Data to DQS Read Timing ParametersDDR Data to DQS Read Timing Parameters Data Valid Figure 33. DDR-Data-to-DQS-WriteTiming ParametersDDR Data to DQS Write Timing Parameters DataDDR-Clock-to-DQS-WriteTiming Parameters 7.1.3Printed Circuit Board Layer StackupFigure 35. Printed Circuit Board Layer Stackup 7.1.4Printed Circuit Board Controlled ImpedanceFebruary Figure 31 on page -Table 29 on page 7.1.5Timing Relationships—Table 30 on page —Table 31 on page Figure 32 on page -Table 30 on page7.1.7Routing Guidelines 7.1.6Resistive Compensation Register Rcomp7.1.7.1Clock Group Clock Signal Group Routing Guidelines 7.1.7.2Data, Command, and Control Groups7.2.1Clock Group 7.2Simulation ResultsDocument Number: 305261, Revision: FebruaryFebruary 7.2.2Data GroupTL1 Tpd = 175 ps/in February Figure 39. DDR Data Topology Two-Bankx16 DevicesDocument Number: 305261, Revision: FebruaryFebruary Document Number 305261, Revision February7.2.3Control Group Document Number 305261, Revision FebruaryTL1 Tpd = 175 ps/in 7.2.4Command GroupTL2 Tpd = 175 ps/in TL3 Tpd = 175 ps/inDocument Number 305261, Revision FebruaryFebruary Document Number 305261, Revision FebruaryFebruary Figure 49. DDR RCVENIN/RCVENOUT Topology 7.2.5RCVENIN and RCVENOUTFebruary Document Number 305261, Revision FebruaryDocument Number 305261, Revision February