High-Speed, Serial Interface, HSSTXDATA0, HSSTXCLK0 | Intel IXP46X

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware Design Considerations

3.10.1Signal Interface

Table 17.		High-Speed, Serial Interface 0

			Input	Pull
	Name		Input	Up	Recommendations
	Name		Output	Up	Recommendations
			Output	Down

					Transmit frame.
HSS_TXFRAME0			I/O	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

					Transmit data out. Open Drain Output.
HSS_TXDATA0			OD	Yes	When this interface/signal is enabled and is either used or not used in a system design,
					the interface/signal should be pulled high with a 10-KΩresistor to VCCP.
					Transmit clock.
HSS_TXCLK0			I/O	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

					Receive frame.
HSS_RXFRAME0			I/O	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

					Receive data input.
HSS_RXDATA0			I	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

					Receive clock.
HSS_RXCLK0			I/O	Yes	When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

Notes:
1.	Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after
	being disabled without asserting a system reset.
2.	Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left
	unconnected.
3.	Features Enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in Note 1 — only require
	pull-ups or pull-downs in the clock-input signals.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
44	Document Number: 305261; Revision: 004

Image 44

Intel IXP46X, IXP45X manual High-Speed, Serial Interface, HSSTXDATA0, HSSTXCLK0, HSSRXDATA0, HSSRXCLK0

Contents

Hardware Design Guidelines February HDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics Tables Revision History Date Revision Description HDD Content Overview Chapter Name Description Related Documentation Title Document # Term Explanation OverviewList of Acronyms and Abbreviations Smii Intel IXP465 Component Block Diagram Typical Applications Dslam System Architecture Description System Memory Map Intel IXP465 Example System Block Diagram Symbol Description Soft Fusible FeaturesSignal Type Definitions Signal Interface Soft Fusible FeaturesDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1 DDR Sdram Interface Pin Description Sheet 2 DdriwenDdrircveninn Ddrircomp DDR Sdram Initialization Expansion BusDDR Sdram Memory Interface Input Pull Name Recommendations Output Down Reset Configuration StrapsExpansion Bus Signal Recommendations Boot/Reset Strapping Configuration Sheet 1 Name Function Description 4 16-Bit Device Interface Boot/Reset Strapping Configuration Sheet 23 8-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface Example Design Notes Uart InterfaceSram Interface Uart Signal Recommendations Name Input Pull Recommendations Output Down MII/SMII Interface Uart Interface Example MII NPE B Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal Recommendations NPE A,B,C MAC Management Signal Recommendations NPE A,B,CDevice Connection, MII Signal Interface, Smii Smii Signal Recommendations NPE A, B, C Gpio Interface Device Connection, Smii Gpio Signal Recommendations Device Connection I2C Signal RecommendationsI2C Interface USB Interface I2C Eeprom Interface Example USB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface Example Utopia Signal Recommendations HSS Interface Utopia Interface Example High-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0 HSSTXDATA1 HSSTXCLK1HSSRXDATA1 HSSRXCLK1 SSP Interface HSS Interface Example Synchronous Serial Peripheral Port Interface Input Pull Name Outpu Recommendations Down PCI InterfacePCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2 Supporting 5 V PCI Interface PCI Interface PCI Option Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3 Clock Signals Clock SignalsInput System Clock Clock Oscillator Name Nominal Description Voltage PowerPower Interface Sheet 1 Power Sequence Reset TimingDe-Coupling Capacitance Recommendations VCC De-Coupling HDD HDD Component Placement PCB OverviewGeneral Recommendations Component Selection Component Placement on a PCB Stack-Up Selection Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout Guidelines Signal Changing Reference Planes General Component Spacing Good Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGA USB Considerations Smii Signal ConsiderationsMII Signal Considerations Cross-Talk EMI-Design Considerations Power and Ground Plane Trace Impedance HDD Electrical Interface Topology@33 MHz @66 MHz Parameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines Trace Length Limits PCI Clock Routing Guidelines Signal Loading Routing Guidelines DDR Signal Groups Group Signal Name Description No of Single Ended SignalsIntroduction DDRIDQS40 DDR Sdram HDD Supported Memory Configurations Clock Banks Memory Size VTT Selecting VTT Power Supply VTT Terminating Circuitry Ddrmclk DDR Command and Control Setup and Hold ValuesSymbol Parameter Min Max Units DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Resistive Compensation Register Rcomp Clock Group Clock Signal Group Routing Guidelines Data, Command, and Control Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Group Topology Transmission Line Characteristics Simulation ResultsClock Group Transmission Line Length DDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 Devices Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control Group DDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line Characteristics DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Topology DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108