Good Design Practice for VIA Hole Placement | Intel IXP45X, IXP46X

General Layout and Routing Guide—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Figure 23. Good Design Practice for VIA Hole Placement

25 mils min

25 mils min

25 mils min

B2266-01

Figure 23 and Figure 24 show good and poor design practices for via placement on surface-mount boards.

Figure 25 shows minimum pad-to-pad clearance for surface-mount passive components and PGA or BGA components.

Figure 24. Poor Design Practice for VIA Placement

Flush Via min

Potential Bridge min

B2267-01

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	65

Image 65

Intel IXP45X, IXP46X manual Good Design Practice for VIA Hole Placement

Contents

February Hardware Design Guidelines HDD Contents 12.1 Figures Tables Control Group Topology Transmission Line Characteristics Date Revision Description Revision History HDD Chapter Name Description Content Overview Title Document # Related Documentation Term Explanation OverviewList of Acronyms and Abbreviations Smii Intel IXP465 Component Block Diagram Dslam Typical Applications System Memory Map System Architecture Description Intel IXP465 Example System Block Diagram Symbol Description Soft Fusible FeaturesSignal Type Definitions Soft Fusible Features Signal InterfaceDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1 Ddriwen DDR Sdram Interface Pin Description Sheet 2Ddrircveninn Ddrircomp DDR Sdram Initialization Expansion BusDDR Sdram Memory Interface Input Pull Name Recommendations Output Down Reset Configuration StrapsExpansion Bus Signal Recommendations Name Function Description Boot/Reset Strapping Configuration Sheet 1 4 16-Bit Device Interface Boot/Reset Strapping Configuration Sheet 23 8-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash Interface Design Notes Uart InterfaceSram Interface Name Input Pull Recommendations Output Down Uart Signal Recommendations Uart Interface Example MII/SMII Interface MII NPE B Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2 NPE A,B,C MAC Management Signal Recommendations NPE A,B,CDevice Connection, MII Smii Signal Recommendations NPE A, B, C Signal Interface, Smii Device Connection, Smii Gpio Interface Gpio Signal Recommendations Device Connection I2C Signal RecommendationsI2C Interface I2C Eeprom Interface Example USB Interface USB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 Interface Utopia Signal Recommendations Utopia Interface Example HSS Interface HSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0 HSSTXCLK1 HSSTXDATA1HSSRXDATA1 HSSRXCLK1 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface Input Pull Name Outpu Recommendations Down PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block Diagram PCI Interface Supporting 5 V PCI Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Option Interface PCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Signals Clock SignalsInput System Clock Clock Oscillator Name Nominal Description Voltage PowerPower Interface Sheet 1 Reset Timing Power SequenceDe-Coupling Capacitance Recommendations VCC De-Coupling HDD HDD PCB Overview Component PlacementGeneral Recommendations Component Selection Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations USB Considerations Smii Signal ConsiderationsMII Signal Considerations EMI-Design Considerations Cross-Talk Trace Impedance Power and Ground Plane HDD Topology Electrical Interface@33 MHz @66 MHz Parameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading Group Signal Name Description No of Single Ended Signals DDR Signal GroupsIntroduction DDRIDQS40 DDR Sdram HDD Clock Banks Memory Size Supported Memory Configurations VTT VTT Terminating Circuitry Selecting VTT Power Supply Ddrmclk DDR Command and Control Setup and Hold ValuesSymbol Parameter Min Max Units DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Clock Group Resistive Compensation Register Rcomp Data, Command, and Control Group Routing Guidelines Clock Signal Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Simulation Results Clock Group Topology Transmission Line CharacteristicsClock Group Transmission Line Length DDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data Group Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line Characteristics DDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command Group DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108