Introduction, DDR Signal Groups, DDRIDQS40 | Intel IXP45X, IXP46X

DDR-SDRAM—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

7.0DDR-SDRAM

7.1Introduction

This document is intended to be used as a guide for routing DDR, based on the Intel® IXDP465 Development Platform. It contains routing guidelines and simulation results for using x16 Thin Small Outline Package (TSOP) memory devices soldered onto the processor module.

As shown in Figure 28, the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors support two banks of 32-bit wide non-Error Correcting Code (non-ECC) or 40-bit wide (ECC) DDR-266 memory with the ability for single-bit error correction or multi-bit error detection (ECC). The IXP45X/IXP46X network processors support un- buffered DRAM only in densities of 128/256/512 Mbit or 1 Gbit. Table 27 lists the signal groups used for the DDR interface.

In this document, the term IXP45X/IXP46X product line refers to both the IXP46X network processors (with DDR ECC) and IXP45X network processors (without DDR ECC).

Table 27.	DDR Signal Groups

	Group	Signal Name	Description	No of Single
	Group	Signal Name	Description	Ended Signals
				Ended Signals

	Clocks	DDRI_CK[2:0]	DDR-SDRAM Differential Clocks	0

		DDRI_CK_N[2:0]	DDR-SDRAM Inverted Differential Clocks	0
		DDRI_CK_N[2:0]	DDR-SDRAM Inverted Differential Clocks	0

		DDRI_CB[7:0]	ECC Data	8

	Data	DDRI_DQ[31:0]	Data Bus	32

		DDRI_DQS[4:0]	Data Strobes	5
		DDRI_DQS[4:0]	Data Strobes	5

		DDRI_DM[4:0]	Data Mask	5

	Control	DDRI_CKE[1:0]	Clock Enable - one per bank	2

		DDRI_CS_N[1:0]	Chip Select - one per bank	2
		DDRI_CS_N[1:0]	Chip Select - one per bank	2

		DDRI_MA[13:0]	Address Bus	14

		DDRI_BA[1:0]	Bank Select	2

	Command	DDRI_RAS_N	Row Address Select	1

		DDRI_CAS_N	Column Address Select	1

		DDRI_WE_N	Write Enable	1

			Total	73

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261, Revision: 004	75

Image 75

Intel IXP45X, IXP46X Introduction, DDR Signal Groups, Group Signal Name Description No of Single Ended Signals, DDRIDQS40

Contents

February Hardware Design Guidelines HDD Contents 12.1 Figures Tables Control Group Topology Transmission Line Characteristics Date Revision Description Revision History HDD Chapter Name Description Content Overview Title Document # Related Documentation Overview List of Acronyms and AbbreviationsTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical Applications System Memory Map System Architecture Description Intel IXP465 Example System Block Diagram Soft Fusible Features Signal Type DefinitionsSymbol Description DDR Sdram Interface Pin Description Sheet 1 Signal InterfaceSoft Fusible Features DDR-266 Sdram Interface Ddrircomp DDR Sdram Interface Pin Description Sheet 2Ddriwen Ddrircveninn Expansion Bus DDR Sdram Memory InterfaceDDR Sdram Initialization Reset Configuration Straps Expansion Bus Signal RecommendationsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 1 Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface4 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash Interface Uart Interface Sram InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal Recommendations Uart Interface Example MII/SMII Interface Signal Interface MII MII NPE a Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE A,B,C Device Connection, MIINPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, Smii Device Connection, Smii Gpio Interface Gpio Signal Recommendations I2C Signal Recommendations I2C InterfaceDevice Connection I2C Eeprom Interface Example USB Interface USB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 Interface Utopia Signal Recommendations Utopia Interface Example HSS Interface HSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0 HSSRXCLK1 HSSTXDATA1HSSTXCLK1 HSSRXDATA1 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface PCI Interface PCI Controller Sheet 1Input Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block Diagram PCI Interface Supporting 5 V PCI Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Option Interface PCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Oscillator Clock SignalsClock Signals Input System Clock Power Power Interface Sheet 1Name Nominal Description Voltage VCC De-Coupling Power SequenceReset Timing De-Coupling Capacitance Recommendations HDD HDD Component Selection Component PlacementPCB Overview General Recommendations Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations Smii Signal Considerations MII Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-Talk Trace Impedance Power and Ground Plane HDD @66 MHz Electrical InterfaceTopology @33 MHz Clock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading DDRIDQS40 DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals Introduction DDR Sdram HDD Clock Banks Memory Size Supported Memory Configurations VTT VTT Terminating Circuitry Selecting VTT Power Supply DDR Command and Control Setup and Hold Values Symbol Parameter Min Max UnitsDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Controlled Impedance Signal Group Absolute Minimum Absolute Maximum Length Timing RelationshipsTiming Relationships Clock Group Resistive Compensation Register Rcomp DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines Parameter Definition Transmission Line Length Clock Group Topology Transmission Line CharacteristicsSimulation Results Clock Group DDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data Group Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line Characteristics DDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command Group DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108