Data Group | Intel IXP46X, IXP45X specification

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

Figure 38. DDR Clock Simulation Results: Two-Bank x16 Devices

The differential-clock-circuit simulation in Figure 38 shows that the voltage waveform meets the DDR device input voltage requirements. The crossing point for the clock input must occur between Vix(min) =1.05 V and Vix(max) =1.45 V and have a minimum peak to peak swing of 700 mV. The receiver input waveform must also not exceed a maximum voltage of Vin(max) =2.8 V or the minimum voltage of Vin(min) =-0.3 V.

Waveform results for device DDR_DEVICE2 is not shown as it is identical to that of device DDR_DEVICE1 due to symmetry. When final routing data is available, simulation results for all receivers are analyzed as variations in routing may result in differences. These differences should be minimal.

7.2.2Data Group

The data signal group includes the signals DDRI_CB[7:0], DDRI_DQ[31:0],

DDRI_DQS[4:0], and DDRI_DM[4:0]. The following simulations were constructed for the 2 bank x16 device configuration where each signal would have two receivers where only one is active for a read or write.

Table 37 identifies the transmission line lengths for the data (DDRI_DQ5) topology shown in Figure 39 on page 94. These lengths were chosen as realistic goals given the IXP45X/IXP46X network processors to DDR device body to body separation of no more than 500 mils.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
92	Document Number: 305261, Revision: 004

Image 92

Intel IXP46X, IXP45X manual Data Group, DDR Clock Simulation Results Two-Bank x16 Devices

Contents

Hardware Design Guidelines February HDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics Tables Revision History Date Revision Description HDD Content Overview Chapter Name Description Related Documentation Title Document # Term Explanation OverviewList of Acronyms and Abbreviations Smii Intel IXP465 Component Block Diagram Typical Applications Dslam System Architecture Description System Memory Map Intel IXP465 Example System Block Diagram Symbol Description Soft Fusible FeaturesSignal Type Definitions Signal Interface Soft Fusible FeaturesDDR-266 Sdram Interface DDR Sdram Interface Pin Description Sheet 1 DDR Sdram Interface Pin Description Sheet 2 DdriwenDdrircveninn Ddrircomp DDR Sdram Initialization Expansion BusDDR Sdram Memory Interface Input Pull Name Recommendations Output Down Reset Configuration StrapsExpansion Bus Signal Recommendations Boot/Reset Strapping Configuration Sheet 1 Name Function Description 4 16-Bit Device Interface Boot/Reset Strapping Configuration Sheet 23 8-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface Example Design Notes Uart InterfaceSram Interface Uart Signal Recommendations Name Input Pull Recommendations Output Down MII/SMII Interface Uart Interface Example MII NPE B Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal Recommendations NPE A,B,C MAC Management Signal Recommendations NPE A,B,CDevice Connection, MII Signal Interface, Smii Smii Signal Recommendations NPE A, B, C Gpio Interface Device Connection, Smii Gpio Signal Recommendations Device Connection I2C Signal RecommendationsI2C Interface USB Interface I2C Eeprom Interface Example USB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface Example Utopia Signal Recommendations HSS Interface Utopia Interface Example High-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0 HSSTXDATA1 HSSTXCLK1HSSRXDATA1 HSSRXCLK1 SSP Interface HSS Interface Example Synchronous Serial Peripheral Port Interface Input Pull Name Outpu Recommendations Down PCI InterfacePCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2 Supporting 5 V PCI Interface PCI Interface PCI Option Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3 Clock Signals Clock SignalsInput System Clock Clock Oscillator Name Nominal Description Voltage PowerPower Interface Sheet 1 Power Sequence Reset TimingDe-Coupling Capacitance Recommendations VCC De-Coupling HDD HDD Component Placement PCB OverviewGeneral Recommendations Component Selection Component Placement on a PCB Stack-Up Selection Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout Guidelines Signal Changing Reference Planes General Component Spacing Good Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGA USB Considerations Smii Signal ConsiderationsMII Signal Considerations Cross-Talk EMI-Design Considerations Power and Ground Plane Trace Impedance HDD Electrical Interface Topology@33 MHz @66 MHz Parameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines Trace Length Limits PCI Clock Routing Guidelines Signal Loading Routing Guidelines DDR Signal Groups Group Signal Name Description No of Single Ended SignalsIntroduction DDRIDQS40 DDR Sdram HDD Supported Memory Configurations Clock Banks Memory Size VTT Selecting VTT Power Supply VTT Terminating Circuitry Ddrmclk DDR Command and Control Setup and Hold ValuesSymbol Parameter Min Max Units DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Resistive Compensation Register Rcomp Clock Group Clock Signal Group Routing Guidelines Data, Command, and Control Group Routing GuidelinesParameter Definition DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Group Topology Transmission Line Characteristics Simulation ResultsClock Group Transmission Line Length DDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 Devices Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control Group DDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line Characteristics DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Topology DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108