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Intel IXP46X, IXP45X manual 3.11SSP Interface, 3.10.2Device Connection, HSS Interface Example

Models: IXP45X IXP46X

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3.10.2Device Connection

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware Design Considerations

3.10.2Device Connection

Figure 14 shows a typical interface between the IXP45X/IXP46X product line and a SLIC CODEC, via the SSP and HSS ports, and a couple of GPIO signals.

Figure 14. HSS Interface Example

Intel®IXP46X		Vccp (3.3 V)
Product Line of	External Oscillator
Network Processors			10 KΩ
GPIO_0
GPIO_1	Clock derived internally
	Clock derived internally
	from 3.6864 MHz
SSP_EXTCLK	or external oscilator
SSP_EXTCLK	33 MHz
	33 MHz	RESET_N	INT_N
		RESET_N	INT_N

SSP_SCLK

CLK

SSP_SFRM

CS_N

SSP_TXD

D I

SSP_RXD

DO

Vccp (3.3 V)

SSP Interface

10 KΩ

HSS_TX_FRAME0

DTX

HSS_TXDATA0

HSS_TXCLK0

HSS_RXFRAME0

FSYNC

HSS_RXDATA0

RXD

HSS_RXCLK0

PCLK

Vccp (3.3 V)

Clock derived from

SLIC/CODEC

10 KΩ

or external oscilator SLIC CODEC

HSS_TX_FRAME1

Unused

HSS_TXDATA1

512 KHz to

HSS_TXCLK1

8.192 MHz

HSS

HSS_RXFRAME1

HSS_RXDATA1

HSS_RXCLK1

HSS Interface

KΩ

KΩ

KΩ

KΩ

KΩ

Vccp (3.3 V)

10

10

10

10

10

AFE

RJ11

B4108-003

3.11SSP Interface

The IXP45X/IXP46X network processors have a Synchronous Serial Peripheral Interface (SSP) module. Its primary function is to provide connectivity between the Intel XScale processor and an external SSP interface.

The SSP module supports National Microwire*, Texas Instruments* synchronous serial protocol (SSP), and Motorola* serial peripheral interface (SPI).

The clock rate can be selected from an internal, 3.6864-MHz source or external source fed at input pin SSP_EXTCLK. The clock can then be divided down anywhere from

7.2KHz to 1.84 MHz by setting bits 15:08 in Control Register 0. For more information, see the SSP configuration registers in the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
46	Document Number: 305261; Revision: 004

Image 46

Intel IXP46X, IXP45X manual 3.11SSP Interface, 3.10.2Device Connection, HSS Interface Example

Contents

February Hardware Design GuidelinesDocument No 305261 Revision February Contents Introduction6.0 PCI Interface Design Considerations February5.0 General Layout and Routing Guide Document Number 305261, RevisionFigures Tables Revision Revision HistoryDate DescriptionFebruary 1.1Content Overview 1.0Introduction1.2Related Documentation 1.4Overview 1.3Acronyms and AbbreviationsList of Acronyms and Abbreviations 32-bitPCI interface Master/Target 33/66 MHz Cryptography Figure 1. Intel IXP465 Component Block DiagramMII/SMII Unit1.5Typical Applications 2.1System Architecture Description 2.0System Architecture2.2System Memory Map Line of Network JTAGIntelIXP46X Product Processors3.0General Hardware Design Considerations 3.1Soft Fusible FeaturesSignal Type Definitions Table3.2DDR-266SDRAM Interface 3.2.1Signal InterfaceSoft Fusible Features DDR SDRAM Interface Pin Description Sheet 1 ofDDR SDRAM Interface Pin Description Sheet 2 of 3.2.2DDR SDRAM Memory Interface 3.3Expansion Bus3.2.3DDR SDRAM Initialization 3.3.2Reset Configuration Straps 3.3.1Signal InterfaceExpansion Bus Signal Recommendations Name Boot/Reset Strapping Configuration Sheet 1 ofTable Function3.3.38-BitDevice Interface Boot/Reset Strapping Configuration Sheet 2 of3.3.416-BitDevice Interface 3.3.532-BitDevice Interface 32-Bit-WordAccess Byte Access16-Bit-WordAccess 8-BitDevice32-Bit-WordAccess Byte Access16-Bit-WordAccess 8-BitDeviceFigure 5. Flash Interface Example Intel Flash3.3.6Flash Interface 16-Bit-WordAccess3.3.8Design Notes 3.4UART Interface3.3.7SRAM Interface Figure 6. Expansion Bus SRAM Interface3.4.1Signal Interface UART Signal RecommendationsFigure 7. UART Interface Example ConnectorMII/SMII Interface UART InterfaceMII NPE A Signal Recommendations 3.5.1Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 of MII NPE B Signal Recommendations Sheet 2 of MII NPE C Signal RecommendationsFigure 8. MII Interface Example 3.5.2Device Connection, MII10/100 3.5.3Signal Interface, SMII 3.5.4Device Connection, SMII 3.6GPIO InterfaceFigure 9. SMII Interface Example GPIO Signal Recommendations 3.6.1Signal Interface3.6.2Design Notes 3.7I2C Interface 3.7.1Signal InterfaceI2C Signal Recommendations 3.7.2Device ConnectionProduct Line 3.8USB InterfaceFigure 10. I2C EEPROM Interface Example Network Processor3.8.1Signal Interface USB Host/Device Signal RecommendationsHost 3.8.2Device ConnectionFigure 11. USB Host Down Stream Interface Example DeviceDevice 3.9UTOPIA Level 2 InterfaceFigure 12. USB Device Interface Example HostUTOPIA Signal Recommendations 3.9.1Signal Interface3.9.2Device Connection Analog Front 3.10HSS InterfaceFigure 13. UTOPIA Interface Example ATM Layer Device3.10.1Signal Interface High-Speed,Serial InterfaceHigh-Speed,Serial Interface Transmit frame3.10.2Device Connection 3.11SSP InterfaceFigure 14. HSS Interface Example Synchronous Serial Peripheral Port Interface 3.11.1Signal Interface3.11.2Device Connection SPI Flash3.12PCI Interface 3.12.1Signal InterfacePCI Controller Sheet 1 of 3.12.2PCI Interface Block Diagram PCI Controller Sheet 2 ofCompact PCI Bus 3.12.3Supporting 5 V PCI InterfaceFigure 16. PCI Interface cPCI J1PCI Device 3.12.4PCI Option Interface3.3V Logic PCI DevicePage 3.13JTAG Interface 3.12.5Design NotesClock Signals 3.13.1Signal Interface3.14.1Clock Signals 3.14Input System Clock3.14.3Device Connection 3.15PowerIntel IXP46X Power Interface Sheet 2 of 3.15.5Power Sequence3.15.6Reset Timing 3.15.1De-CouplingCapacitance RecommendationsFebruary Document Number 305261 RevisionFebruary Document Number 305261 Revision4.1PCB Overview 4.4Component Placement4.0General PCB Guide 4.2General RecommendationsInexpensive Figure 19. Component Placement on a PCB4.5Stack-UpSelection Medium FrequencyHigher cost More weight Uncontrolled signal trace impedanceLow-impedancepower distribution Poor routing densityFigure 20. 8-LayerStackup Figure 21. 6-LayerStackup5.1Overview 5.0General Layout and Routing Guide5.2General Layout Guidelines 5.2.1General Component Spacing Figure 22. Signal Changing Reference PlanesVIAs 25 mils min 25 mils min 25 mils min Figure 24. Poor Design Practice for VIA PlacementFlush Via min Potential Bridge min 5.2.2Clock Signal Considerations PGA or BGA Package5.2.4MII Signal Considerations 5.2.3SMII Signal Considerations5.2.5USB Considerations 5.2.6Cross-Talk 5.2.7EMI-DesignConsiderationsFebruary 5.2.9Power and Ground Plane5.2.8Trace Impedance Document Number 305261 RevisionFebruary Document Number 305261 Revision6.1Electrical Interface 6.0PCI Interface Design Considerations6.2Topology PCI Slot 6.3Clock DistributionFigure 26. PCI Address/Data Topology Table 25. PCI Address/Data Routing GuidelinesClock 6.3.1Trace Length LimitsPCI Devices Driver6.3.2Routing Guidelines 6.3.3Signal LoadingFebruary 7.1Introduction DDR Signal Groups7.0DDR-SDRAM TableLine of Network Figure 28. Processor-DDRInterfaceProcessors DDR SDRAMFebruary Document Number: 305261, Revision:Supported Memory Configurations Termination VTT Signal TerminationSignal Intel IXP46XIXP46X 7.1.1Selecting VTT Power SupplyFigure 30. VTT Terminating Circuitry DDR SDRAMDDR M CLK Figure 31. DDR Command and Control Setup and HoldControl/Command Valid 7.1.2Signal-TimingAnalysisData Figure 32. DDR Data to DQS Read Timing ParametersDDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters Figure 33. DDR-Data-to-DQS-WriteTiming ParametersData Valid Data7.1.3Printed Circuit Board Layer Stackup DDR-Clock-to-DQS-WriteTiming Parameters7.1.4Printed Circuit Board Controlled Impedance Figure 35. Printed Circuit Board Layer StackupFebruary —Table 30 on page —Table 31 on page 7.1.5Timing RelationshipsFigure 31 on page -Table 29 on page Figure 32 on page -Table 30 on page7.1.7Routing Guidelines 7.1.6Resistive Compensation Register Rcomp7.1.7.1Clock Group 7.1.7.2Data, Command, and Control Groups Clock Signal Group Routing Guidelines7.2Simulation Results 7.2.1Clock GroupFebruary Document Number: 305261, Revision:7.2.2Data Group FebruaryTL1 Tpd = 175 ps/in Figure 39. DDR Data Topology Two-Bankx16 Devices FebruaryFebruary Document Number: 305261, Revision:February February Document Number 305261, Revision7.2.3Control Group February Document Number 305261, RevisionTL2 Tpd = 175 ps/in 7.2.4Command GroupTL1 Tpd = 175 ps/in TL3 Tpd = 175 ps/inFebruary Document Number 305261, RevisionFebruary February Document Number 305261, RevisionFebruary 7.2.5RCVENIN and RCVENOUT Figure 49. DDR RCVENIN/RCVENOUT TopologyFebruary February Document Number 305261, RevisionFebruary Document Number 305261, Revision