SSP Interface, HSS Interface Example | Intel IXP46X, IXP45X instruction

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware Design Considerations

3.10.2Device Connection

Figure 14 shows a typical interface between the IXP45X/IXP46X product line and a SLIC CODEC, via the SSP and HSS ports, and a couple of GPIO signals.

Figure 14. HSS Interface Example

Intel®IXP46X		Vccp (3.3 V)
Product Line of	External Oscillator
Network Processors			10 KΩ
GPIO_0
GPIO_1	Clock derived internally
	Clock derived internally
	from 3.6864 MHz
SSP_EXTCLK	or external oscilator
SSP_EXTCLK	33 MHz
	33 MHz	RESET_N	INT_N
		RESET_N	INT_N

SSP_SCLK

CLK

SSP_SFRM

CS_N

SSP_TXD

D I

SSP_RXD

DO

Vccp (3.3 V)

SSP Interface

10 KΩ

HSS_TX_FRAME0

DTX

HSS_TXDATA0

HSS_TXCLK0

HSS_RXFRAME0

FSYNC

HSS_RXDATA0

RXD

HSS_RXCLK0

PCLK

Vccp (3.3 V)

Clock derived from

SLIC/CODEC

10 KΩ

or external oscilator SLIC CODEC

HSS_TX_FRAME1

Unused

HSS_TXDATA1

512 KHz to

HSS_TXCLK1

8.192 MHz

HSS

HSS_RXFRAME1

HSS_RXDATA1

HSS_RXCLK1

HSS Interface

KΩ

KΩ

KΩ

KΩ

KΩ

Vccp (3.3 V)

10

10

10

10

10

AFE

RJ11

B4108-003

3.11SSP Interface

The IXP45X/IXP46X network processors have a Synchronous Serial Peripheral Interface (SSP) module. Its primary function is to provide connectivity between the Intel XScale processor and an external SSP interface.

The SSP module supports National Microwire*, Texas Instruments* synchronous serial protocol (SSP), and Motorola* serial peripheral interface (SPI).

The clock rate can be selected from an internal, 3.6864-MHz source or external source fed at input pin SSP_EXTCLK. The clock can then be divided down anywhere from

7.2KHz to 1.84 MHz by setting bits 15:08 in Control Register 0. For more information, see the SSP configuration registers in the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Developer’s Manual.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
46	Document Number: 305261; Revision: 004

Image 46

Intel IXP46X, IXP45X manual SSP Interface, HSS Interface Example

Contents

Hardware Design Guidelines February HDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics Tables Revision History Date Revision Description HDD Content Overview Chapter Name Description Related Documentation Title Document # List of Acronyms and Abbreviations OverviewTerm Explanation Smii Intel IXP465 Component Block Diagram Typical Applications Dslam System Architecture Description System Memory Map Intel IXP465 Example System Block Diagram Signal Type Definitions Soft Fusible FeaturesSymbol Description DDR-266 Sdram Interface Signal InterfaceSoft Fusible Features DDR Sdram Interface Pin Description Sheet 1 Ddrircveninn DDR Sdram Interface Pin Description Sheet 2Ddriwen Ddrircomp DDR Sdram Memory Interface Expansion BusDDR Sdram Initialization Expansion Bus Signal Recommendations Reset Configuration StrapsInput Pull Name Recommendations Output Down Boot/Reset Strapping Configuration Sheet 1 Name Function Description 3 8-Bit Device Interface Boot/Reset Strapping Configuration Sheet 24 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface Example Sram Interface Uart InterfaceDesign Notes Uart Signal Recommendations Name Input Pull Recommendations Output Down MII/SMII Interface Uart Interface Example MII NPE a Signal Recommendations Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal Recommendations Device Connection, MII MAC Management Signal Recommendations NPE A,B,CNPE A,B,C Signal Interface, Smii Smii Signal Recommendations NPE A, B, C Gpio Interface Device Connection, Smii Gpio Signal Recommendations I2C Interface I2C Signal RecommendationsDevice Connection USB Interface I2C Eeprom Interface Example USB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface Example Utopia Signal Recommendations HSS Interface Utopia Interface Example HSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0 HSSRXDATA1 HSSTXDATA1HSSTXCLK1 HSSRXCLK1 SSP Interface HSS Interface Example Synchronous Serial Peripheral Port Interface PCI Controller Sheet 1 PCI InterfaceInput Pull Name Outpu Recommendations Down PCI Interface Block Diagram PCI Controller Sheet 2 Supporting 5 V PCI Interface PCI Interface PCI Option Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3 Input System Clock Clock SignalsClock Signals Clock Oscillator Power Interface Sheet 1 PowerName Nominal Description Voltage De-Coupling Capacitance Recommendations Power SequenceReset Timing VCC De-Coupling HDD HDD General Recommendations Component PlacementPCB Overview Component Selection Component Placement on a PCB Stack-Up Selection Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout Guidelines Signal Changing Reference Planes General Component Spacing Good Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGA MII Signal Considerations Smii Signal ConsiderationsUSB Considerations Cross-Talk EMI-Design Considerations Power and Ground Plane Trace Impedance HDD @33 MHz Electrical InterfaceTopology @66 MHz PCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines Trace Length Limits PCI Clock Routing Guidelines Signal Loading Routing Guidelines Introduction DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals DDRIDQS40 DDR Sdram HDD Supported Memory Configurations Clock Banks Memory Size VTT Selecting VTT Power Supply VTT Terminating Circuitry Symbol Parameter Min Max Units DDR Command and Control Setup and Hold ValuesDdrmclk DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Resistive Compensation Register Rcomp Clock Group Parameter Definition Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Group Clock Group Topology Transmission Line CharacteristicsSimulation Results Transmission Line Length DDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 Devices Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control Group DDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line Characteristics DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Topology DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108