Intel IXP46X, IXP45X manual 3.2DDR-266SDRAM Interface, 3.2.1Signal Interface, Soft Fusible Features

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware Design Considerations

Table 3.	Soft Fusible Features
	Name	Description
	PCI	The complete bus must be enabled or disable.
	HSS0/1	Can only be disable as a pair.
	UTOPIA	If enabling UTOPIA, MACs on NPE A are disabled.
		If enabling MACs on NPE A, UTOPIA are disabled.
	ETHERNET	Can Enable either MII MACs or SMII MACs, but not both at the same time. Enable of MACs
		can be separately done per each NPE.
	USB Host	Each USB can be Enable separately.
	USB Device	Each USB can be Enable separately.
	DDR ECC	DDR can be disabled separately form the rest of the DDR interface.

3.2DDR-266 SDRAM Interface

The IXP45X/IXP46X network processors support unbuffered, DDR-266 SDRAM technology, capable of addressing two memory banks (one bank per CS). Each bank can be configured to support 32/64/128/256/512-Mbyte for a total combined memory support of 1 Gbyte.

The device supports non-ECC and ECC for error correction, which can be enable or disable by software as required. Banks have a bus width of 32 bits for non ECC or 40 bits for ECC enable (32-bit data + 8-bit ECC).

For a complete feature list, see the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet.

General DDR SDRAM routing guidelines can be found in Section 7.1.7, “Routing Guidelines” on page 88. For more detailed information, see the PC266 DDR SDRAM specification.

3.2.1Signal Interface

Table 4.	DDR SDRAM Interface Pin Description (Sheet 1 of 2)
		Input		VTT
Name		Outpu	Device-Pin Connection	Terminatio	Description
		t		n
			Connect a pair of differential clock
DDRI_CK[2:0]		O	signals to every device; When		DDR SDRAM Clock Out — Provides the positive
			using both banks, daisy chain	No	differential clocks to the external SDRAM
			devices with same data bit		memory subsystem.
			sequence.
					DDR SDRAM Clock Out — Provides the
DDRI_CK_N[2:0]		O	Same as above	No	negative differential clocks to the external
					SDRAM memory subsystem.
			Use the same CS to control 32-bit		Chip Select — Must be asserted for all
DDRI_CS_N[1:0]		O		Yes	transactions to the DDR SDRAM device. One
			data + 8-bit ECC, per bank
					per bank.
			The RAS signal must be connected		Row Address Strobe — Indicates that the
DDRI_RAS_N		O	to each device in a daisy chain	Yes
					current address on DDRI_MA[13:0] is the row.
			manner
			The CAS signal must be connected		Column Address Strobe — Indicates that the
DDRI_CAS_N		O	to each device in a daisy chain	Yes	current address on DDRI_MA[13:0] is the
			manner		column.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
18	Document Number: 305261; Revision: 004