PCI Interface Design
Network Processors
6.0PCI Interface Design Considerations
The Intel® IXP45X and Intel® IXP46X Product Line of Network Processors has a single,
The PCI module is compatible with the PCI Local Bus Specification, Rev. 2.2. For a complete functional description and physical requirements, see PCI Local Bus Specification, Rev. 2.2.
6.1Electrical Interface
The electrical definition is restricted to 3.3 V signaling environment. The device is not 5 V tolerant. All devices interfacing with the PCI module need to operate at 3.3 V.
6.2Topology
Interfacing devices need to be connected in a
There is a limitation to the number of devices connected to the internal arbiter. If more than four devices are required to be connected, an external arbiter is required.
The system time budget must be satisfied for 66 MHz and 33 MHz cycles. It is expected that if the timing budget for 66 MHz clock cycles is satisfied, then the 33 MHz cycles also work. The following equation and timing parameters need to be met when routing a board that either interfaces to a single PCI device or up to four devices as shown in Figure 26.
TCYC ≥ TVAL +TPROP + TSKEW + TSU
where:
TVAL = Valid Output Delay
TPROP = Bus Propagation Delay (maximum time for complete flight) TSKEW = Total Clock Skew
TSU = Input Setup Time
@33 MHz | TCYC = 30 nSec | TVAL = 11 nSec | TPROP = 10 nSec | TSKEW = 2 nSec | TSU = 7 nSec |
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@66 MHz | TCYC = 15 nSec | TVAL = 6 nSec | TPROP = 5 nSec | TSKEW = 1 nSec | TSU = 3 nSec |
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When defining the maximum length of segments A and B as shown in Figure 26, the calculation must:
•Include an additional trace length segment from the PCI connector to the input device within the expansion PCI card.
•Assume the segment to be 1.5 inch.
•Use trace propagation delay of 150 to 190 ps/in as specified by the PCI standard.
| Intel® IXP45X and Intel® IXP46X Product Line of Network Processors |
February 2007 | HDD |
Document Number: 305261, Revision: 004 | 71 |