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Intel IXP45X, IXP46X manual February, Document Number 305261, Revision

Models: IXP45X IXP46X

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DDR-SDRAM—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Figure 51. DDR RCVENIN/RCVENOUT Simulation Results (Rseries = 60 Ω)

The simulation results in Figure 51 are for the RCVENIN/RCVENOUT circuit, the voltage waveform meets the DDR device input voltage requirements. Vil(max) of Vref – 0.150 or 1.10 V and Vih(min) of Vref + 0.150 or 1.40 V are easily achieved at the receiver (RCVENIN). The receiver waveform must also not exceed a maximum voltage of Vin(max) = 2.8 V or the minimum voltage of Vin(min) = -0.3 V.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261, Revision: 004	107

Page 107

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Intel IXP45X, IXP46X manual February, Document Number 305261, Revision

Contents

Document No 305261 Revision Hardware Design GuidelinesFebruary February Introduction ContentsDocument Number 305261, Revision February5.0 General Layout and Routing Guide 6.0 PCI Interface Design ConsiderationsFigures Tables Description Revision HistoryDate RevisionFebruary 1.0Introduction 1.1Content Overview1.2Related Documentation List of Acronyms and Abbreviations 1.3Acronyms and Abbreviations1.4Overview 32-bitPCI interface Master/Target 33/66 MHz Unit Figure 1. Intel IXP465 Component Block DiagramMII/SMII Cryptography1.5Typical Applications 2.2System Memory Map 2.0System Architecture2.1System Architecture Description Processors JTAGIntelIXP46X Product Line of NetworkTable 3.1Soft Fusible FeaturesSignal Type Definitions 3.0General Hardware Design ConsiderationsDDR SDRAM Interface Pin Description Sheet 1 of 3.2.1Signal InterfaceSoft Fusible Features 3.2DDR-266SDRAM InterfaceDDR SDRAM Interface Pin Description Sheet 2 of 3.2.3DDR SDRAM Initialization 3.3Expansion Bus3.2.2DDR SDRAM Memory Interface Expansion Bus Signal Recommendations 3.3.1Signal Interface3.3.2Reset Configuration Straps Function Boot/Reset Strapping Configuration Sheet 1 ofTable Name3.3.416-BitDevice Interface Boot/Reset Strapping Configuration Sheet 2 of3.3.38-BitDevice Interface 3.3.532-BitDevice Interface 8-BitDevice Byte Access16-Bit-WordAccess 32-Bit-WordAccess8-BitDevice Byte Access16-Bit-WordAccess 32-Bit-WordAccess16-Bit-WordAccess Intel Flash3.3.6Flash Interface Figure 5. Flash Interface ExampleFigure 6. Expansion Bus SRAM Interface 3.4UART Interface3.3.7SRAM Interface 3.3.8Design NotesUART Signal Recommendations 3.4.1Signal InterfaceUART Interface ConnectorMII/SMII Interface Figure 7. UART Interface ExampleMII NPE B Signal Recommendations Sheet 1 of 3.5.1Signal Interface MIIMII NPE A Signal Recommendations MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2 of10/100 3.5.2Device Connection, MIIFigure 8. MII Interface Example 3.5.3Signal Interface, SMII Figure 9. SMII Interface Example 3.6GPIO Interface3.5.4Device Connection, SMII 3.6.2Design Notes 3.6.1Signal InterfaceGPIO Signal Recommendations 3.7.2Device Connection 3.7.1Signal InterfaceI2C Signal Recommendations 3.7I2C InterfaceNetwork Processor 3.8USB InterfaceFigure 10. I2C EEPROM Interface Example Product LineUSB Host/Device Signal Recommendations 3.8.1Signal InterfaceDevice 3.8.2Device ConnectionFigure 11. USB Host Down Stream Interface Example HostHost 3.9UTOPIA Level 2 InterfaceFigure 12. USB Device Interface Example Device3.9.2Device Connection 3.9.1Signal InterfaceUTOPIA Signal Recommendations ATM Layer Device 3.10HSS InterfaceFigure 13. UTOPIA Interface Example Analog FrontHigh-Speed,Serial Interface 3.10.1Signal InterfaceTransmit frame High-Speed,Serial InterfaceFigure 14. HSS Interface Example 3.11SSP Interface3.10.2Device Connection SPI Flash 3.11.1Signal Interface3.11.2Device Connection Synchronous Serial Peripheral Port InterfacePCI Controller Sheet 1 of 3.12.1Signal Interface3.12PCI Interface PCI Controller Sheet 2 of 3.12.2PCI Interface Block DiagramcPCI J1 3.12.3Supporting 5 V PCI InterfaceFigure 16. PCI Interface Compact PCI BusPCI Device 3.12.4PCI Option Interface3.3V Logic PCI DevicePage 3.12.5Design Notes 3.13JTAG Interface3.14Input System Clock 3.13.1Signal Interface3.14.1Clock Signals Clock SignalsIntel IXP46X 3.15Power3.14.3Device Connection 3.15.1De-CouplingCapacitance Recommendations 3.15.5Power Sequence3.15.6Reset Timing Power Interface Sheet 2 ofDocument Number 305261 Revision FebruaryDocument Number 305261 Revision February4.2General Recommendations 4.4Component Placement4.0General PCB Guide 4.1PCB OverviewMedium Frequency Figure 19. Component Placement on a PCB4.5Stack-UpSelection InexpensivePoor routing density Uncontrolled signal trace impedanceLow-impedancepower distribution Higher cost More weightFigure 21. 6-LayerStackup Figure 20. 8-LayerStackup5.2General Layout Guidelines 5.0General Layout and Routing Guide5.1Overview VIAs Figure 22. Signal Changing Reference Planes5.2.1General Component Spacing Flush Via min Potential Bridge min Figure 24. Poor Design Practice for VIA Placement25 mils min 25 mils min 25 mils min PGA or BGA Package 5.2.2Clock Signal Considerations5.2.5USB Considerations 5.2.3SMII Signal Considerations5.2.4MII Signal Considerations 5.2.7EMI-DesignConsiderations 5.2.6Cross-TalkDocument Number 305261 Revision 5.2.9Power and Ground Plane5.2.8Trace Impedance FebruaryDocument Number 305261 Revision February6.2Topology 6.0PCI Interface Design Considerations6.1Electrical Interface Table 25. PCI Address/Data Routing Guidelines 6.3Clock DistributionFigure 26. PCI Address/Data Topology PCI SlotDriver 6.3.1Trace Length LimitsPCI Devices ClockFebruary 6.3.3Signal Loading6.3.2Routing Guidelines Table DDR Signal Groups7.0DDR-SDRAM 7.1IntroductionDDR SDRAM Figure 28. Processor-DDRInterfaceProcessors Line of NetworkDocument Number: 305261, Revision: FebruarySupported Memory Configurations Intel IXP46X VTT Signal TerminationSignal TerminationDDR SDRAM 7.1.1Selecting VTT Power SupplyFigure 30. VTT Terminating Circuitry IXP46X7.1.2Signal-TimingAnalysis Figure 31. DDR Command and Control Setup and HoldControl/Command Valid DDR M CLKDDR Data to DQS Read Timing Parameters Figure 32. DDR Data to DQS Read Timing ParametersData Data Figure 33. DDR-Data-to-DQS-WriteTiming ParametersData Valid DDR Data to DQS Write Timing ParametersDDR-Clock-to-DQS-WriteTiming Parameters 7.1.3Printed Circuit Board Layer StackupFigure 35. Printed Circuit Board Layer Stackup 7.1.4Printed Circuit Board Controlled ImpedanceFebruary Figure 32 on page -Table 30 on page 7.1.5Timing RelationshipsFigure 31 on page -Table 29 on page —Table 30 on page —Table 31 on page7.1.7.1Clock Group 7.1.6Resistive Compensation Register Rcomp7.1.7Routing Guidelines Clock Signal Group Routing Guidelines 7.1.7.2Data, Command, and Control Groups7.2.1Clock Group 7.2Simulation ResultsDocument Number: 305261, Revision: FebruaryFebruary 7.2.2Data GroupTL1 Tpd = 175 ps/in February Figure 39. DDR Data Topology Two-Bankx16 DevicesDocument Number: 305261, Revision: FebruaryFebruary Document Number 305261, Revision February7.2.3Control Group Document Number 305261, Revision FebruaryTL3 Tpd = 175 ps/in 7.2.4Command GroupTL1 Tpd = 175 ps/in TL2 Tpd = 175 ps/inDocument Number 305261, Revision FebruaryFebruary Document Number 305261, Revision FebruaryFebruary Figure 49. DDR RCVENIN/RCVENOUT Topology 7.2.5RCVENIN and RCVENOUTFebruary Document Number 305261, Revision FebruaryDocument Number 305261, Revision February