Intel IXP46X, IXP45X manual 3.14Input System Clock, 3.13.1Signal Interface, 3.14.1Clock Signals

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware Design Considerations

3.13.1Signal Interface

Table 22.	Synchronous Serial Peripheral Port Interface
	Input/	Pull
Name		Up/	Recommendations
	Output
		Down
			Test mode select.
JTG_TMS	I	Yes	Ω
			When the JTAG interface is not being used, the signal must be pulled high using a 10-k
			resistor.
			Test Input data.
JTG_TDI	I	Yes	When the JTAG interface is not being used, the signal must be pulled high using a 10-kΩ
			resistor.
JTG_TDO	O	O	Test Output data.
			Test Reset.
JTG_TRST_N	I	Yes	Ω
			When the JTAG interface is not being used, the signal must be pulled low using a 10-k
			resistor.
			Test Clock.
JTG_TCK	I	Yes	When the JTAG interface is not being used, the signal must be pulled high using a 10-kΩ
			resistor.

3.14Input System Clock

The IXP45X/IXP46X network processors require a 33.33-MHz reference clock to generate all internal clocks required — including core clock — and the various buses running internally within the system.

3.14.1Clock Signals

Table 23.	Clock Signals
	Name	Type*	Description
	OSC_IN	I	Source must be a clock input of 33.33-MHz.
			Use a series termination resistor, 10 Ω to 33 Ω at the source.
	OSC_OUT	O	No connect

Note: For explanations of the Type column abbreviations, see Table 2 on page 17.

3.14.2Clock Oscillator

When using an external clock oscillator to supply the 33.33-MHz reference system clock, connect the clock oscillator output to OSC_IN pin through a series termination of 33 Ω as shown in Figure 18. The series termination helps smooth the rise and fall edges of the clock and eliminate ringing. Leave the OSC_OUT pin un-connected.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
54	Document Number: 305261; Revision: 004