Flash Interface Example | Intel IXP45X, IXP46X specification

General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

3.3.6Flash Interface

Figure 5 illustrates how a boot ROM is connected to the expansion bus. The flash (ROM) used in the block diagram is the Intel StrataFlash® memory device TE28F256J3D — 32-Mbyte, 16-bit, flash in the 56-TSOP package. The Intel StrataFlash memory TE28F256J3D is part of the 0.13-micron, 3.3-V Intel StrataFlash memory.

The E28F256J3D supports common flash interface (CFI). For information on migrating from J3 to J3D Intel StrataFlash memory, see the Intel StrataFlash® Memory J3 to Intel® Embedded Flash Memory (J3 v.D) Conversion Guide - Application Note 835 (document 308555).

For information on migrating from J3 to P30 Intel StrataFlash memory, see the Migration Guide for Intel StrataFlash® Memory (J3) to Intel StrataFlash® Embedded Memory (P30 and P33) - Application Note 835 (document 308555).

The example in Figure 5 shows a 16-bit flash memory device connected to the IXP45X/ IXP46X network processors. Boot-strapping is required in the address bus, both EX_ADDR[0] and EX_ADDR[7] need external, 4.7-KΩpull-down resistors (not shown on diagram). The pull-down resistors sets Bits 0 and 7 low in the Configuration Register

0.This in turn sets the processor into a 16-bit-mode access.

Figure 5. Flash Interface Example

	EX_DATA[31:0]	EX_DATA[15:0]		DATA[15:0]
	Intel® IXP46X			16-Bit Device
	Product Line of			16-Bit Device
	Network Processors	EX_ADDR[24:0]		16-Bit-Word Access
	EX_ADDR[24:0]	EX_ADDR[24:0]		ADDR[24:0]
	EX_ADDR[24:0]			ADDR[24:0]
	EX_CS_N	CS		CE0
	EX_RD_N	OE		OE_N
	EX_WR_N	WR		WR_N
		3.3 V	RST#	Intel® Flash
			RST#	RP_N
				CE1
	4.7 KΩ	4.7 KΩ		CE2
				BYTE_N
				VPEN_N
				4.7 KΩ
				B4097- 003

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	27

Image 27

Intel IXP45X, IXP46X manual Flash Interface Example

Contents

February Hardware Design Guidelines HDD Contents 12.1 Figures Tables Control Group Topology Transmission Line Characteristics Date Revision Description Revision History HDD Chapter Name Description Content Overview Title Document # Related Documentation Overview List of Acronyms and AbbreviationsTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical Applications System Memory Map System Architecture Description Intel IXP465 Example System Block Diagram Soft Fusible Features Signal Type DefinitionsSymbol Description DDR Sdram Interface Pin Description Sheet 1 Signal InterfaceSoft Fusible Features DDR-266 Sdram Interface Ddrircomp DDR Sdram Interface Pin Description Sheet 2Ddriwen Ddrircveninn Expansion Bus DDR Sdram Memory InterfaceDDR Sdram Initialization Reset Configuration Straps Expansion Bus Signal RecommendationsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 1 Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface4 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash Interface Uart Interface Sram InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal Recommendations Uart Interface Example MII/SMII Interface Signal Interface MII MII NPE a Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE A,B,C Device Connection, MIINPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, Smii Device Connection, Smii Gpio Interface Gpio Signal Recommendations I2C Signal Recommendations I2C InterfaceDevice Connection I2C Eeprom Interface Example USB Interface USB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 Interface Utopia Signal Recommendations Utopia Interface Example HSS Interface HSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0 HSSRXCLK1 HSSTXDATA1HSSTXCLK1 HSSRXDATA1 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface PCI Interface PCI Controller Sheet 1Input Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block Diagram PCI Interface Supporting 5 V PCI Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Option Interface PCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Oscillator Clock SignalsClock Signals Input System Clock Power Power Interface Sheet 1Name Nominal Description Voltage VCC De-Coupling Power SequenceReset Timing De-Coupling Capacitance Recommendations HDD HDD Component Selection Component PlacementPCB Overview General Recommendations Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations Smii Signal Considerations MII Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-Talk Trace Impedance Power and Ground Plane HDD @66 MHz Electrical InterfaceTopology @33 MHz Clock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading DDRIDQS40 DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals Introduction DDR Sdram HDD Clock Banks Memory Size Supported Memory Configurations VTT VTT Terminating Circuitry Selecting VTT Power Supply DDR Command and Control Setup and Hold Values Symbol Parameter Min Max UnitsDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Controlled Impedance Signal Group Absolute Minimum Absolute Maximum Length Timing RelationshipsTiming Relationships Clock Group Resistive Compensation Register Rcomp DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines Parameter Definition Transmission Line Length Clock Group Topology Transmission Line CharacteristicsSimulation Results Clock Group DDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data Group Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line Characteristics DDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command Group DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108