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Intel IXP45X Intel Flash, 3.3.6Flash Interface, Flash Interface Example, BitDevice, Intel IXP46X

Models: IXP45X IXP46X

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3.3.6Flash Interface

General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

3.3.6Flash Interface

Figure 5 illustrates how a boot ROM is connected to the expansion bus. The flash (ROM) used in the block diagram is the Intel StrataFlash® memory device TE28F256J3D — 32-Mbyte, 16-bit, flash in the 56-TSOP package. The Intel StrataFlash memory TE28F256J3D is part of the 0.13-micron, 3.3-V Intel StrataFlash memory.

The E28F256J3D supports common flash interface (CFI). For information on migrating from J3 to J3D Intel StrataFlash memory, see the Intel StrataFlash® Memory J3 to Intel® Embedded Flash Memory (J3 v.D) Conversion Guide - Application Note 835 (document 308555).

For information on migrating from J3 to P30 Intel StrataFlash memory, see the Migration Guide for Intel StrataFlash® Memory (J3) to Intel StrataFlash® Embedded Memory (P30 and P33) - Application Note 835 (document 308555).

The example in Figure 5 shows a 16-bit flash memory device connected to the IXP45X/ IXP46X network processors. Boot-strapping is required in the address bus, both EX_ADDR[0] and EX_ADDR[7] need external, 4.7-KΩpull-down resistors (not shown on diagram). The pull-down resistors sets Bits 0 and 7 low in the Configuration Register

0.This in turn sets the processor into a 16-bit-mode access.

Figure 5. Flash Interface Example

	EX_DATA[31:0]	EX_DATA[15:0]		DATA[15:0]
	Intel® IXP46X			16-Bit Device
	Product Line of			16-Bit Device
	Network Processors	EX_ADDR[24:0]		16-Bit-Word Access
	EX_ADDR[24:0]	EX_ADDR[24:0]		ADDR[24:0]
	EX_ADDR[24:0]			ADDR[24:0]
	EX_CS_N	CS		CE0
	EX_RD_N	OE		OE_N
	EX_WR_N	WR		WR_N
		3.3 V	RST#	Intel® Flash
			RST#	RP_N
				CE1
	4.7 KΩ	4.7 KΩ		CE2
				BYTE_N
				VPEN_N
				4.7 KΩ
				B4097- 003

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	27

Image 27

Intel IXP45X Intel Flash, 3.3.6Flash Interface, Flash Interface Example, BitDevice, Network Processors, Bit-WordAccess

Contents

Hardware Design Guidelines FebruaryDocument No 305261 Revision February Introduction ContentsDocument Number 305261, Revision February5.0 General Layout and Routing Guide 6.0 PCI Interface Design ConsiderationsFigures Tables Description Revision HistoryDate RevisionFebruary 1.0Introduction 1.1Content Overview1.2Related Documentation 1.3Acronyms and Abbreviations 1.4OverviewList of Acronyms and Abbreviations 32-bitPCI interface Master/Target 33/66 MHz Unit Figure 1. Intel IXP465 Component Block DiagramMII/SMII Cryptography1.5Typical Applications 2.0System Architecture 2.1System Architecture Description2.2System Memory Map Processors JTAGIntelIXP46X Product Line of NetworkTable 3.1Soft Fusible FeaturesSignal Type Definitions 3.0General Hardware Design ConsiderationsDDR SDRAM Interface Pin Description Sheet 1 of 3.2.1Signal InterfaceSoft Fusible Features 3.2DDR-266SDRAM InterfaceDDR SDRAM Interface Pin Description Sheet 2 of 3.3Expansion Bus 3.2.2DDR SDRAM Memory Interface3.2.3DDR SDRAM Initialization 3.3.1Signal Interface 3.3.2Reset Configuration StrapsExpansion Bus Signal Recommendations Function Boot/Reset Strapping Configuration Sheet 1 ofTable NameBoot/Reset Strapping Configuration Sheet 2 of 3.3.38-BitDevice Interface3.3.416-BitDevice Interface 3.3.532-BitDevice Interface 8-BitDevice Byte Access16-Bit-WordAccess 32-Bit-WordAccess8-BitDevice Byte Access16-Bit-WordAccess 32-Bit-WordAccess16-Bit-WordAccess Intel Flash3.3.6Flash Interface Figure 5. Flash Interface ExampleFigure 6. Expansion Bus SRAM Interface 3.4UART Interface3.3.7SRAM Interface 3.3.8Design NotesUART Signal Recommendations 3.4.1Signal InterfaceUART Interface ConnectorMII/SMII Interface Figure 7. UART Interface Example3.5.1Signal Interface MII MII NPE A Signal RecommendationsMII NPE B Signal Recommendations Sheet 1 of MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2 of3.5.2Device Connection, MII Figure 8. MII Interface Example10/100 3.5.3Signal Interface, SMII 3.6GPIO Interface 3.5.4Device Connection, SMIIFigure 9. SMII Interface Example 3.6.1Signal Interface GPIO Signal Recommendations3.6.2Design Notes 3.7.2Device Connection 3.7.1Signal InterfaceI2C Signal Recommendations 3.7I2C InterfaceNetwork Processor 3.8USB InterfaceFigure 10. I2C EEPROM Interface Example Product LineUSB Host/Device Signal Recommendations 3.8.1Signal InterfaceDevice 3.8.2Device ConnectionFigure 11. USB Host Down Stream Interface Example HostHost 3.9UTOPIA Level 2 InterfaceFigure 12. USB Device Interface Example Device3.9.1Signal Interface UTOPIA Signal Recommendations3.9.2Device Connection ATM Layer Device 3.10HSS InterfaceFigure 13. UTOPIA Interface Example Analog FrontHigh-Speed,Serial Interface 3.10.1Signal InterfaceTransmit frame High-Speed,Serial Interface3.11SSP Interface 3.10.2Device ConnectionFigure 14. HSS Interface Example SPI Flash 3.11.1Signal Interface3.11.2Device Connection Synchronous Serial Peripheral Port Interface3.12.1Signal Interface 3.12PCI InterfacePCI Controller Sheet 1 of PCI Controller Sheet 2 of 3.12.2PCI Interface Block DiagramcPCI J1 3.12.3Supporting 5 V PCI InterfaceFigure 16. PCI Interface Compact PCI BusPCI Device 3.12.4PCI Option Interface3.3V Logic PCI DevicePage 3.12.5Design Notes 3.13JTAG Interface3.14Input System Clock 3.13.1Signal Interface3.14.1Clock Signals Clock Signals3.15Power 3.14.3Device ConnectionIntel IXP46X 3.15.1De-CouplingCapacitance Recommendations 3.15.5Power Sequence3.15.6Reset Timing Power Interface Sheet 2 ofDocument Number 305261 Revision FebruaryDocument Number 305261 Revision February4.2General Recommendations 4.4Component Placement4.0General PCB Guide 4.1PCB OverviewMedium Frequency Figure 19. Component Placement on a PCB4.5Stack-UpSelection InexpensivePoor routing density Uncontrolled signal trace impedanceLow-impedancepower distribution Higher cost More weightFigure 21. 6-LayerStackup Figure 20. 8-LayerStackup5.0General Layout and Routing Guide 5.1Overview5.2General Layout Guidelines Figure 22. Signal Changing Reference Planes 5.2.1General Component SpacingVIAs Figure 24. Poor Design Practice for VIA Placement 25 mils min 25 mils min 25 mils minFlush Via min Potential Bridge min PGA or BGA Package 5.2.2Clock Signal Considerations5.2.3SMII Signal Considerations 5.2.4MII Signal Considerations5.2.5USB Considerations 5.2.7EMI-DesignConsiderations 5.2.6Cross-TalkDocument Number 305261 Revision 5.2.9Power and Ground Plane5.2.8Trace Impedance FebruaryDocument Number 305261 Revision February6.0PCI Interface Design Considerations 6.1Electrical Interface6.2Topology Table 25. PCI Address/Data Routing Guidelines 6.3Clock DistributionFigure 26. PCI Address/Data Topology PCI SlotDriver 6.3.1Trace Length LimitsPCI Devices Clock6.3.3Signal Loading 6.3.2Routing GuidelinesFebruary Table DDR Signal Groups7.0DDR-SDRAM 7.1IntroductionDDR SDRAM Figure 28. Processor-DDRInterfaceProcessors Line of NetworkDocument Number: 305261, Revision: FebruarySupported Memory Configurations Intel IXP46X VTT Signal TerminationSignal TerminationDDR SDRAM 7.1.1Selecting VTT Power SupplyFigure 30. VTT Terminating Circuitry IXP46X7.1.2Signal-TimingAnalysis Figure 31. DDR Command and Control Setup and HoldControl/Command Valid DDR M CLKFigure 32. DDR Data to DQS Read Timing Parameters DataDDR Data to DQS Read Timing Parameters Data Figure 33. DDR-Data-to-DQS-WriteTiming ParametersData Valid DDR Data to DQS Write Timing ParametersDDR-Clock-to-DQS-WriteTiming Parameters 7.1.3Printed Circuit Board Layer StackupFigure 35. Printed Circuit Board Layer Stackup 7.1.4Printed Circuit Board Controlled ImpedanceFebruary Figure 32 on page -Table 30 on page 7.1.5Timing RelationshipsFigure 31 on page -Table 29 on page —Table 30 on page —Table 31 on page7.1.6Resistive Compensation Register Rcomp 7.1.7Routing Guidelines7.1.7.1Clock Group Clock Signal Group Routing Guidelines 7.1.7.2Data, Command, and Control Groups7.2.1Clock Group 7.2Simulation ResultsDocument Number: 305261, Revision: FebruaryFebruary 7.2.2Data GroupTL1 Tpd = 175 ps/in February Figure 39. DDR Data Topology Two-Bankx16 DevicesDocument Number: 305261, Revision: FebruaryFebruary Document Number 305261, Revision February7.2.3Control Group Document Number 305261, Revision FebruaryTL3 Tpd = 175 ps/in 7.2.4Command GroupTL1 Tpd = 175 ps/in TL2 Tpd = 175 ps/inDocument Number 305261, Revision FebruaryFebruary Document Number 305261, Revision FebruaryFebruary Figure 49. DDR RCVENIN/RCVENOUT Topology 7.2.5RCVENIN and RCVENOUTFebruary Document Number 305261, Revision FebruaryDocument Number 305261, Revision February