Intel IXP46X, IXP45X manual Supported Memory Configurations, Clock Banks Memory Size

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

Table 28.	Supported Memory Configurations
	DDR	Device	Number of	Devices	Number of	Devices	Number	Total
	Device		DDR Devices	per	DDR Devices	per
	Density	Width	(non-ECC)	Clock	(ECC)	Clock	of Banks	Memory Size
	128 Mbit	x8	4	2,2	5	2,2,1	1	64 Mbyte
	128 Mbit	x8	8	Driver	10	Driver	2	128 Mbyte
	128 Mbit	x16	2	1,1	3	1,1,1	1	32 Mbyte
	128 Mbit	x16	4	2,2	6	2,2,2	2	64 Mbyte
	256 Mbit	x8	4	2,2	5	2,2,1	1	128 Mbyte
	256 Mbit	x8	8	Driver	10	Driver	2	256 Mbyte
	256 Mbit	x16	2	1,1	3	1,1,1	1	64 Mbyte
	256 Mbit	x16	4	2,2	6	2,2,2	2	128 Mbyte
	512 Mbit	x8	4	2,2	5	2,2,1	1	256 Mbyte
	512 Mbit	x8	8	Driver	10	Driver	2	512 Mbyte
	512 Mbit	x16	2	1,1	3	1,1,1	1	128 Mbyte
	512 Mbit	x16	4	2,2	6	2,2,2	2	256 Mbyte
	1 Gbit	x8	4	2,2	5	2,2,1	1	512 Mbyte
	1 Gbit	x8	8	Driver	10	Driver	2	1 Gbyte
	1 Gbit	x16	2	1,1	3	1,1,1	1	256 Mbyte
	1 Gbit	x16	4	2,2	6	2,2,2	2	512 Mbyte

Figure 29 shows the DDR memory interface of the IXP45X/IXP46X network processors using x16 devices with Error Correcting Code (ECC). Bank 0 is represented by DDR devices 1, 3, and 5. Bank 1 is represented by DDR devices 2, 4, and 6. Unused data inputs on the ECC devices (5 and 6) are pulled to ground through 10-KΩresistors.

The VTT signal termination used for all signals, except clocks, is a series 60.4-Ωresistor to a 1.25-V DC power supply designed for DDR memory termination. The appropriate value for termination resistance should be verified through simulation for the specific topology as shown in “Simulation Results” on page 90. The supply chosen for this application was the TPS54672 from Texas Instruments*.

The DDRI_RCVENOUT_N signal must be connected to the DDRI_RCVENIN_N signal with a trace which is propagation delay length matched to the average delay of the clock (DDRI_CK[2:0]) plus data (DDRI_DQ[31:0]). A series terminating resistor (Rs) should be used to control overshoot and undershoot, as shown in Figure 49 on page 105.

A resistance value in the 25- to 50-Ωrange should be used as it adds minimal propagation delay to the signal without adversely varying from the CLK plus DQ propagation delay average. The appropriate value for termination resistance should be verified through simulation for the specific topology.

The DDRI_RCOMP signal must be terminated through a 20-Ω, 1%, 0.1-W resistor (Rcomp) to ground. This allows the DDR controller to make temperature and process adjustments.

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
78	Document Number: 305261, Revision: 004