Intel IXP46X, IXP45X manual DDR Data to DQS Read Timing Parameters

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

Figure 32. DDR Data to DQS Read Timing Parameters

T1
T4
T7	T2
T3
DQS
Data
D0	D1
	T8
T6
T5
	B3989-001

Table 30.	DDR Data to DQS Read Timing Parameters
	Symbol		Parameter	Min	Max	Units	Notes
	T1		IXP45X/IXP46X network processors delay for data group		0.75	ns	1
			valid after any edge of DQS
	T2		IXP45X/IXP46X network processors guaranteed time		1.0	ns	1
			before data group begins to transition invalid prior to DQS
	T3		Data valid window for IXP45X/IXP46X network processors	2.0		ns	1
	T4		DQ-DQS skew, DQS to last data group signal going valid		0.5	ns	1
			from DDR memory device
	T5		DQ-DQS hold, DQS to first data group signal going non-	3.0		ns	1
			valid from DDR memory device
	T6		Data valid window from DDR memory device	2.5		ns	1
	T7		Allowable data group to DQS difference for data going		0.25	ns	1
			valid (T1 - T4)
	T8		Allowable data group to DQS difference for data going		0.25	ns	1
			invalid (T5 - T3 - T1)
	Notes:
	1.	Data group signals consist of DDRI_DM[4:0], DDRI_DQ[31:0], and DDRI_CB[7:0].

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
82	Document Number: 305261, Revision: 004