Power Interface Sheet 1 | Intel IXP45X, IXP46X manual

General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

3.14.3Device Connection

Figure 18. Clock Oscillator Interface Example

				3.3 V
	OSC_IN	OUT	VDD
	OSC_IN	33 Ω	VDD	10 KΩ
		33 Ω	ON	10 KΩ
			ON
				0.01 µF
			33.33 MHz
	OSC_OUT
	Intel® IXP46X
	Product Line of
	Network Processors
				B4111 -001

3.15Power

To enable low power system design, the IXP45X/IXP46X network processors have separate power supply domains for the processor core, DDR SDRAM memory, and input/output peripherals.

Table 24. Power Interface (Sheet 1 of 2)

	Name	Nominal	Description
	Name	Voltage	Description
		Voltage

			Core supply voltage.
	VCC	1.3 V	Note: If operating at 667MHz, core supply voltage must be increased to VCC = 1.5 V. For details, see
			the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet.
	VCCP	3.3 V	I/O supply voltage.

	VCCM	2.5 V	DDR memory interface supply voltage.

	VSS	GND	Ground for supply voltages 3.3 V, 2.5 V, and 1.3/1.5 V.

			Supply voltage for peripheral (I/O) logic of analog oscillator circuitry.
	OSC_VCCP	3.3 V	Require special power filtering circuitry. See the Intel® IXP45X and Intel® IXP46X Product Line of
			Network Processors Datasheet.

			Ground for peripheral (I/O) logic of analog oscillator circuitry. Used in conjunction with the OSC_VCCP
	OSC_VSSP	GND	pins.
	OSC_VSSP	GND	Require special power filtering circuitry. See the Intel® IXP45X and Intel® IXP46X Product Line of

			Network Processors Datasheet.

			Supply voltage for internal logic of the analog oscillator circuitry. Requires special power filtering
	OSC_VCC	1.3 V	circuitry. If operating at 667 MHz, this voltage must be increased to 1.5 V.
			See the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet.
			Ground for internal logic of the analog oscillator circuitry. Used in conjunction with the OSC_VCC pins.
	OSC_VSS	GND	Require special power filtering circuitry. See the Intel® IXP45X and Intel® IXP46X Product Line of
			Network Processors Datasheet.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	55

Image 55

Intel IXP45X, IXP46X manual Power Interface Sheet 1, Name Nominal Description Voltage

Contents

February Hardware Design Guidelines HDD Contents 12.1 Figures Tables Control Group Topology Transmission Line Characteristics Date Revision Description Revision History HDD Chapter Name Description Content Overview Title Document # Related Documentation List of Acronyms and Abbreviations OverviewTerm Explanation Smii Intel IXP465 Component Block Diagram Dslam Typical Applications System Memory Map System Architecture Description Intel IXP465 Example System Block Diagram Signal Type Definitions Soft Fusible FeaturesSymbol Description DDR Sdram Interface Pin Description Sheet 1 Signal InterfaceSoft Fusible Features DDR-266 Sdram Interface Ddrircomp DDR Sdram Interface Pin Description Sheet 2Ddriwen Ddrircveninn DDR Sdram Memory Interface Expansion BusDDR Sdram Initialization Expansion Bus Signal Recommendations Reset Configuration StrapsInput Pull Name Recommendations Output Down Name Function Description Boot/Reset Strapping Configuration Sheet 1 3 8-Bit Device Interface Boot/Reset Strapping Configuration Sheet 24 16-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash Interface Sram Interface Uart InterfaceDesign Notes Name Input Pull Recommendations Output Down Uart Signal Recommendations Uart Interface Example MII/SMII Interface MII NPE a Signal Recommendations Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2 Device Connection, MII MAC Management Signal Recommendations NPE A,B,CNPE A,B,C Smii Signal Recommendations NPE A, B, C Signal Interface, Smii Device Connection, Smii Gpio Interface Gpio Signal Recommendations I2C Interface I2C Signal RecommendationsDevice Connection I2C Eeprom Interface Example USB Interface USB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 Interface Utopia Signal Recommendations Utopia Interface Example HSS Interface HSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0 HSSRXCLK1 HSSTXDATA1HSSTXCLK1 HSSRXDATA1 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface PCI Controller Sheet 1 PCI InterfaceInput Pull Name Outpu Recommendations Down PCI Controller Sheet 2 PCI Interface Block Diagram PCI Interface Supporting 5 V PCI Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Option Interface PCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Oscillator Clock SignalsClock Signals Input System Clock Power Interface Sheet 1 PowerName Nominal Description Voltage VCC De-Coupling Power SequenceReset Timing De-Coupling Capacitance Recommendations HDD HDD Component Selection Component PlacementPCB Overview General Recommendations Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations MII Signal Considerations Smii Signal ConsiderationsUSB Considerations EMI-Design Considerations Cross-Talk Trace Impedance Power and Ground Plane HDD @66 MHz Electrical InterfaceTopology @33 MHz PCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading DDRIDQS40 DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals Introduction DDR Sdram HDD Clock Banks Memory Size Supported Memory Configurations VTT VTT Terminating Circuitry Selecting VTT Power Supply Symbol Parameter Min Max Units DDR Command and Control Setup and Hold ValuesDdrmclk DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Clock Group Resistive Compensation Register Rcomp DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines Parameter Definition Transmission Line Length Clock Group Topology Transmission Line CharacteristicsSimulation Results Clock Group DDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data Group Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line Characteristics DDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command Group DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108