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Intel IXP45X, IXP46X 3.10HSS Interface, UTOPIA Interface Example, Analog Front, ATM Layer Device

Models: IXP45X IXP46X

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Figure 13. UTOPIA Interface Example

General Hardware Design Considerations—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

Figure 13. UTOPIA Interface Example

Intel® IXP45X/46X
Product Line
Network Processor	Control Signals
EX_BUS	Control Signals
EX_BUS
			Analog Front
ATM Layer Device	25 MHz	ADSL Framer	End
		Multi-Channel	AFE	RJ11
UTP_OP_CLK		TXCLK
UTP_OP_FCO		TXENB#
UTP_OP_ADDR[4:0]		TXADDR[4:0]
UTP_OP_FCI		TXCLAV
UTP_OP_SOC		TXSOC
UTP_OP_DATA[7:0]		TXDATA[7:0]
UTP_IP_FCO		RXENB#
UTP_IP_ADDR[4:0]		RXADDR[4:0]
UTP_IP_FCI		RXCLAV
UTP_IP_SOC		RXSOC
UTP_IP_DATA[7:0]		RXDATA[7:0]	AFE	RJ11
UTP_IP_CLK		RXCLK	AFE	RJ11
UTP_IP_CLK		RXCLK
UTOPIA Level 2
Interface	25 MHz
	25 MHz	SDRAM
		SDRAM
		Local Memory
				B4107 -003

3.10HSS Interface

NPE A has an integrated High-Speed Serial (HSS) module, whose primary function is to provide connectivity between the internal NPE A and the external HSS interface. There are two HSS ports that can directly interface to SLIC/CODEC devices for voice applications, or serial DSL framers. The HSS ports are software configurable to support various serial protocols, such as T1/ E1/J1, and MVIP. For a list of supported protocols, see the Intel® IXP400 Software Programmer’s Guide.

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
February 2007	HDD
Document Number: 305261; Revision: 004	43

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Intel IXP45X manual 3.10HSS Interface, UTOPIA Interface Example, Analog Front, ATM Layer Device, ADSL Framer, Multi-Channel

Contents

February Hardware Design GuidelinesDocument No 305261 Revision February Introduction ContentsDocument Number 305261, Revision February5.0 General Layout and Routing Guide 6.0 PCI Interface Design ConsiderationsFigures Tables Description Revision HistoryDate RevisionFebruary 1.0Introduction 1.1Content Overview1.2Related Documentation 1.4Overview 1.3Acronyms and AbbreviationsList of Acronyms and Abbreviations 32-bitPCI interface Master/Target 33/66 MHz Unit Figure 1. Intel IXP465 Component Block DiagramMII/SMII Cryptography1.5Typical Applications 2.1System Architecture Description 2.0System Architecture2.2System Memory Map Processors JTAGIntelIXP46X Product Line of NetworkTable 3.1Soft Fusible FeaturesSignal Type Definitions 3.0General Hardware Design ConsiderationsDDR SDRAM Interface Pin Description Sheet 1 of 3.2.1Signal InterfaceSoft Fusible Features 3.2DDR-266SDRAM InterfaceDDR SDRAM Interface Pin Description Sheet 2 of 3.2.2DDR SDRAM Memory Interface 3.3Expansion Bus3.2.3DDR SDRAM Initialization 3.3.2Reset Configuration Straps 3.3.1Signal InterfaceExpansion Bus Signal Recommendations Function Boot/Reset Strapping Configuration Sheet 1 ofTable Name3.3.38-BitDevice Interface Boot/Reset Strapping Configuration Sheet 2 of3.3.416-BitDevice Interface 3.3.532-BitDevice Interface 8-BitDevice Byte Access16-Bit-WordAccess 32-Bit-WordAccess8-BitDevice Byte Access16-Bit-WordAccess 32-Bit-WordAccess16-Bit-WordAccess Intel Flash3.3.6Flash Interface Figure 5. Flash Interface ExampleFigure 6. Expansion Bus SRAM Interface 3.4UART Interface3.3.7SRAM Interface 3.3.8Design NotesUART Signal Recommendations 3.4.1Signal InterfaceUART Interface ConnectorMII/SMII Interface Figure 7. UART Interface ExampleMII NPE A Signal Recommendations 3.5.1Signal Interface MIIMII NPE B Signal Recommendations Sheet 1 of MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2 ofFigure 8. MII Interface Example 3.5.2Device Connection, MII10/100 3.5.3Signal Interface, SMII 3.5.4Device Connection, SMII 3.6GPIO InterfaceFigure 9. SMII Interface Example GPIO Signal Recommendations 3.6.1Signal Interface3.6.2Design Notes 3.7.2Device Connection 3.7.1Signal InterfaceI2C Signal Recommendations 3.7I2C InterfaceNetwork Processor 3.8USB InterfaceFigure 10. I2C EEPROM Interface Example Product LineUSB Host/Device Signal Recommendations 3.8.1Signal InterfaceDevice 3.8.2Device ConnectionFigure 11. USB Host Down Stream Interface Example HostHost 3.9UTOPIA Level 2 InterfaceFigure 12. USB Device Interface Example DeviceUTOPIA Signal Recommendations 3.9.1Signal Interface3.9.2Device Connection ATM Layer Device 3.10HSS InterfaceFigure 13. UTOPIA Interface Example Analog FrontHigh-Speed,Serial Interface 3.10.1Signal InterfaceTransmit frame High-Speed,Serial Interface3.10.2Device Connection 3.11SSP InterfaceFigure 14. HSS Interface Example SPI Flash 3.11.1Signal Interface3.11.2Device Connection Synchronous Serial Peripheral Port Interface3.12PCI Interface 3.12.1Signal InterfacePCI Controller Sheet 1 of PCI Controller Sheet 2 of 3.12.2PCI Interface Block DiagramcPCI J1 3.12.3Supporting 5 V PCI InterfaceFigure 16. PCI Interface Compact PCI BusPCI Device 3.12.4PCI Option Interface3.3V Logic PCI DevicePage 3.12.5Design Notes 3.13JTAG Interface3.14Input System Clock 3.13.1Signal Interface3.14.1Clock Signals Clock Signals3.14.3Device Connection 3.15PowerIntel IXP46X 3.15.1De-CouplingCapacitance Recommendations 3.15.5Power Sequence3.15.6Reset Timing Power Interface Sheet 2 ofDocument Number 305261 Revision FebruaryDocument Number 305261 Revision February4.2General Recommendations 4.4Component Placement4.0General PCB Guide 4.1PCB OverviewMedium Frequency Figure 19. Component Placement on a PCB4.5Stack-UpSelection InexpensivePoor routing density Uncontrolled signal trace impedanceLow-impedancepower distribution Higher cost More weightFigure 21. 6-LayerStackup Figure 20. 8-LayerStackup5.1Overview 5.0General Layout and Routing Guide5.2General Layout Guidelines 5.2.1General Component Spacing Figure 22. Signal Changing Reference PlanesVIAs 25 mils min 25 mils min 25 mils min Figure 24. Poor Design Practice for VIA PlacementFlush Via min Potential Bridge min PGA or BGA Package 5.2.2Clock Signal Considerations5.2.4MII Signal Considerations 5.2.3SMII Signal Considerations5.2.5USB Considerations 5.2.7EMI-DesignConsiderations 5.2.6Cross-TalkDocument Number 305261 Revision 5.2.9Power and Ground Plane5.2.8Trace Impedance FebruaryDocument Number 305261 Revision February6.1Electrical Interface 6.0PCI Interface Design Considerations6.2Topology Table 25. PCI Address/Data Routing Guidelines 6.3Clock DistributionFigure 26. PCI Address/Data Topology PCI SlotDriver 6.3.1Trace Length LimitsPCI Devices Clock6.3.2Routing Guidelines 6.3.3Signal LoadingFebruary Table DDR Signal Groups7.0DDR-SDRAM 7.1IntroductionDDR SDRAM Figure 28. Processor-DDRInterfaceProcessors Line of NetworkDocument Number: 305261, Revision: FebruarySupported Memory Configurations Intel IXP46X VTT Signal TerminationSignal TerminationDDR SDRAM 7.1.1Selecting VTT Power SupplyFigure 30. VTT Terminating Circuitry IXP46X7.1.2Signal-TimingAnalysis Figure 31. DDR Command and Control Setup and HoldControl/Command Valid DDR M CLKData Figure 32. DDR Data to DQS Read Timing ParametersDDR Data to DQS Read Timing Parameters Data Figure 33. DDR-Data-to-DQS-WriteTiming ParametersData Valid DDR Data to DQS Write Timing ParametersDDR-Clock-to-DQS-WriteTiming Parameters 7.1.3Printed Circuit Board Layer StackupFigure 35. Printed Circuit Board Layer Stackup 7.1.4Printed Circuit Board Controlled ImpedanceFebruary Figure 32 on page -Table 30 on page 7.1.5Timing RelationshipsFigure 31 on page -Table 29 on page —Table 30 on page —Table 31 on page7.1.7Routing Guidelines 7.1.6Resistive Compensation Register Rcomp7.1.7.1Clock Group Clock Signal Group Routing Guidelines 7.1.7.2Data, Command, and Control Groups7.2.1Clock Group 7.2Simulation ResultsDocument Number: 305261, Revision: FebruaryFebruary 7.2.2Data GroupTL1 Tpd = 175 ps/in February Figure 39. DDR Data Topology Two-Bankx16 DevicesDocument Number: 305261, Revision: FebruaryFebruary Document Number 305261, Revision February7.2.3Control Group Document Number 305261, Revision FebruaryTL3 Tpd = 175 ps/in 7.2.4Command GroupTL1 Tpd = 175 ps/in TL2 Tpd = 175 ps/inDocument Number 305261, Revision FebruaryFebruary Document Number 305261, Revision FebruaryFebruary Figure 49. DDR RCVENIN/RCVENOUT Topology 7.2.5RCVENIN and RCVENOUTFebruary Document Number 305261, Revision FebruaryDocument Number 305261, Revision February