16/32-Bit Device Interface Byte Enable | Intel IXP46X, IXP45X

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware Design Considerations

Figure 4. 8/16/32-Bit Device Interface: Byte Enable

EX_DATA[31:0]	EX_DATA[7:0]	DATA[7:0]
Intel® IXP46X		8-Bit Device
Product Line of		8-Bit Device
Network Processors		Byte Access
EX_ADDR[24:0]	EX_ADDR[24:0]	ADDR[24:0]
EX_CS_N	CS	CS_N
EX_RD_N	OE	OE_N
EX_BE_N0	WR0	WR_N
EX_DATA[31:0]	EX_DATA[15:0]	DATA[15:0]
Intel® IXP46X		16-Bit Device
Product Line of		16-Bit Device
Network Processors		16-Bit-Word Access
EX_ADDR[24:0]	EX_ADDR[24:0]	ADDR[24:0]
EX_CS_N	CS	CS_N
EX_RD_N	OE	OE_N
EX_BE_N0	WR0	WR_N0
EX_BE_N1	WR1	WR_N1
EX_DATA[31:0]	EX_DATA[31:0]	DATA[31:0]
Intel® IXP46X		32-Bit Device
Product Line of		32-Bit Device
Network Processors		32-Bit-Word Access
EX_ADDR[24:0]	EX_ADDR[24:0]	ADDR[24:0]
EX_CS_N	CS	CS_N
EX_RD_N	OE	OE_N
EX_BE_N0	WR0	WR_N0
EX_BE_N1	WR1	WR_N1
EX_BE_N2	WR2	WR_N2
EX_BE_N3	WR3	WR_N3
		B4096-003

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
26	Document Number: 305261; Revision: 004

Image 26

Intel IXP46X, IXP45X manual 16/32-Bit Device Interface Byte Enable

Contents

Hardware Design Guidelines February HDD Contents 12.1 Figures Control Group Topology Transmission Line Characteristics Tables Revision History Date Revision Description HDD Content Overview Chapter Name Description Related Documentation Title Document # Term Explanation OverviewList of Acronyms and Abbreviations Smii Intel IXP465 Component Block Diagram Typical Applications Dslam System Architecture Description System Memory Map Intel IXP465 Example System Block Diagram Symbol Description Soft Fusible FeaturesSignal Type Definitions DDR-266 Sdram Interface Signal InterfaceSoft Fusible Features DDR Sdram Interface Pin Description Sheet 1 Ddrircveninn DDR Sdram Interface Pin Description Sheet 2Ddriwen Ddrircomp DDR Sdram Initialization Expansion BusDDR Sdram Memory Interface Input Pull Name Recommendations Output Down Reset Configuration StrapsExpansion Bus Signal Recommendations Boot/Reset Strapping Configuration Sheet 1 Name Function Description 4 16-Bit Device Interface Boot/Reset Strapping Configuration Sheet 23 8-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Flash Interface Example Design Notes Uart InterfaceSram Interface Uart Signal Recommendations Name Input Pull Recommendations Output Down MII/SMII Interface Uart Interface Example MII NPE B Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations MII NPE B Signal Recommendations Sheet 2 MII NPE C Signal Recommendations NPE A,B,C MAC Management Signal Recommendations NPE A,B,CDevice Connection, MII Signal Interface, Smii Smii Signal Recommendations NPE A, B, C Gpio Interface Device Connection, Smii Gpio Signal Recommendations Device Connection I2C Signal RecommendationsI2C Interface USB Interface I2C Eeprom Interface Example USB Host/Device Signal Recommendations Host Device Utopia Level 2 Interface USB Device Interface Example Utopia Signal Recommendations HSS Interface Utopia Interface Example HSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0 HSSRXDATA1 HSSTXDATA1HSSTXCLK1 HSSRXCLK1 SSP Interface HSS Interface Example Synchronous Serial Peripheral Port Interface Input Pull Name Outpu Recommendations Down PCI InterfacePCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2 Supporting 5 V PCI Interface PCI Interface PCI Option Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Host/Option Interface Pin Description Sheet 2 Jtag Interface PCI Host/Option Interface Pin Description Sheet 3 Input System Clock Clock SignalsClock Signals Clock Oscillator Name Nominal Description Voltage PowerPower Interface Sheet 1 De-Coupling Capacitance Recommendations Power SequenceReset Timing VCC De-Coupling HDD HDD General Recommendations Component PlacementPCB Overview Component Selection Component Placement on a PCB Stack-Up Selection Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout Guidelines Signal Changing Reference Planes General Component Spacing Good Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGA USB Considerations Smii Signal ConsiderationsMII Signal Considerations Cross-Talk EMI-Design Considerations Power and Ground Plane Trace Impedance HDD @33 MHz Electrical InterfaceTopology @66 MHz Parameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines Trace Length Limits PCI Clock Routing Guidelines Signal Loading Routing Guidelines Introduction DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals DDRIDQS40 DDR Sdram HDD Supported Memory Configurations Clock Banks Memory Size VTT Selecting VTT Power Supply VTT Terminating Circuitry Ddrmclk DDR Command and Control Setup and Hold ValuesSymbol Parameter Min Max Units DDR Data to DQS Read Timing Parameters DDR-Data-to-DQS-Write Timing Parameters DDR Data to DQS Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Resistive Compensation Register Rcomp Clock Group Parameter Definition Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Group Clock Group Topology Transmission Line CharacteristicsSimulation Results Transmission Line Length DDR Clock Topology Two-Bank x16 Devices Data Group DDR Clock Simulation Results Two-Bank x16 Devices Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Topology Transmission Line Characteristics Control Group DDR RAS Simulation Results Two-Bank x16 Devices Command Group Command Group Topology Transmission Line Characteristics DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Topology DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108