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Intel IXP46X, IXP45X manual 7.1.1Selecting VTT Power Supply, VTT Terminating Circuitry, Ddr Sdram

Models: IXP45X IXP46X

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7.1.1Selecting VTT Power Supply

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—Category

7.1.1Selecting VTT Power Supply

Selecting the minimum power requirement for VTT supply is a simple calculation that varies depending on the resistive value of RVTT terminating resistors. Since all RVTT has the same value, the power calculation becomes a simple, current times voltage times the number of terminating resistors used. Figure 30 shows an example of one terminating network, for which the following equation can be solved for the unknown:

Vout = 0 or 2.5V

VTT=1.25V

RVTT= 60 Ω (we can assume this value)

N = 73 (from Table 27 obtain the total number of RVTT resistors)

P = (V x I) x N= (Vout (- or +) VTT) x (VTT/RVTT) x N

P = (2.5V-1.25V) x (1.25V/60 Ω) x 73

P = 1.9 Watt. Allow a 25% overhead. P = 1.9W + 1.9W x 0.25 = 2.38 Watt

It is very important to allow some overhead for the VTT power supply, just like any other power distribution allow some overhead in case the value of RVTT or simply for inrush current. The following figure shows the diagram of the current paths for the above equation.

Figure 30. VTT Terminating Circuitry

		VTT
		RVTT
IXP46X	Vout	DDR SDRAM
IXP46X		DDR SDRAM

Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD	February 2007
80	Document Number: 305261, Revision: 004

Image 80

Intel IXP46X, IXP45X manual 7.1.1Selecting VTT Power Supply, VTT Terminating Circuitry, Ddr Sdram

Contents

Document No 305261 Revision Hardware Design GuidelinesFebruary February Contents IntroductionFebruary 5.0 General Layout and Routing Guide6.0 PCI Interface Design Considerations Document Number 305261, RevisionFigures Tables Revision History DateRevision DescriptionFebruary 1.1Content Overview 1.0Introduction1.2Related Documentation List of Acronyms and Abbreviations 1.3Acronyms and Abbreviations1.4Overview 32-bitPCI interface Master/Target 33/66 MHz Figure 1. Intel IXP465 Component Block Diagram MII/SMIICryptography Unit1.5Typical Applications 2.2System Memory Map 2.0System Architecture2.1System Architecture Description JTAG IntelIXP46X ProductLine of Network Processors3.1Soft Fusible Features Signal Type Definitions3.0General Hardware Design Considerations Table3.2.1Signal Interface Soft Fusible Features3.2DDR-266SDRAM Interface DDR SDRAM Interface Pin Description Sheet 1 ofDDR SDRAM Interface Pin Description Sheet 2 of 3.2.3DDR SDRAM Initialization 3.3Expansion Bus3.2.2DDR SDRAM Memory Interface Expansion Bus Signal Recommendations 3.3.1Signal Interface3.3.2Reset Configuration Straps Boot/Reset Strapping Configuration Sheet 1 of TableName Function3.3.416-BitDevice Interface Boot/Reset Strapping Configuration Sheet 2 of3.3.38-BitDevice Interface 3.3.532-BitDevice Interface Byte Access 16-Bit-WordAccess32-Bit-WordAccess 8-BitDeviceByte Access 16-Bit-WordAccess32-Bit-WordAccess 8-BitDeviceIntel Flash 3.3.6Flash InterfaceFigure 5. Flash Interface Example 16-Bit-WordAccess3.4UART Interface 3.3.7SRAM Interface3.3.8Design Notes Figure 6. Expansion Bus SRAM Interface3.4.1Signal Interface UART Signal RecommendationsConnector MII/SMII InterfaceFigure 7. UART Interface Example UART InterfaceMII NPE B Signal Recommendations Sheet 1 of 3.5.1Signal Interface MIIMII NPE A Signal Recommendations MII NPE B Signal Recommendations Sheet 2 of MII NPE C Signal Recommendations10/100 3.5.2Device Connection, MIIFigure 8. MII Interface Example 3.5.3Signal Interface, SMII Figure 9. SMII Interface Example 3.6GPIO Interface3.5.4Device Connection, SMII 3.6.2Design Notes 3.6.1Signal InterfaceGPIO Signal Recommendations 3.7.1Signal Interface I2C Signal Recommendations3.7I2C Interface 3.7.2Device Connection3.8USB Interface Figure 10. I2C EEPROM Interface ExampleProduct Line Network Processor3.8.1Signal Interface USB Host/Device Signal Recommendations3.8.2Device Connection Figure 11. USB Host Down Stream Interface ExampleHost Device3.9UTOPIA Level 2 Interface Figure 12. USB Device Interface ExampleDevice Host3.9.2Device Connection 3.9.1Signal InterfaceUTOPIA Signal Recommendations 3.10HSS Interface Figure 13. UTOPIA Interface ExampleAnalog Front ATM Layer Device3.10.1Signal Interface High-Speed,Serial InterfaceHigh-Speed,Serial Interface Transmit frameFigure 14. HSS Interface Example 3.11SSP Interface3.10.2Device Connection 3.11.1Signal Interface 3.11.2Device ConnectionSynchronous Serial Peripheral Port Interface SPI FlashPCI Controller Sheet 1 of 3.12.1Signal Interface3.12PCI Interface 3.12.2PCI Interface Block Diagram PCI Controller Sheet 2 of3.12.3Supporting 5 V PCI Interface Figure 16. PCI InterfaceCompact PCI Bus cPCI J13.12.4PCI Option Interface 3.3V LogicPCI Device PCI DevicePage 3.13JTAG Interface 3.12.5Design Notes3.13.1Signal Interface 3.14.1Clock SignalsClock Signals 3.14Input System ClockIntel IXP46X 3.15Power3.14.3Device Connection 3.15.5Power Sequence 3.15.6Reset TimingPower Interface Sheet 2 of 3.15.1De-CouplingCapacitance RecommendationsFebruary Document Number 305261 RevisionFebruary Document Number 305261 Revision4.4Component Placement 4.0General PCB Guide4.1PCB Overview 4.2General RecommendationsFigure 19. Component Placement on a PCB 4.5Stack-UpSelectionInexpensive Medium FrequencyUncontrolled signal trace impedance Low-impedancepower distributionHigher cost More weight Poor routing densityFigure 20. 8-LayerStackup Figure 21. 6-LayerStackup5.2General Layout Guidelines 5.0General Layout and Routing Guide5.1Overview VIAs Figure 22. Signal Changing Reference Planes5.2.1General Component Spacing Flush Via min Potential Bridge min Figure 24. Poor Design Practice for VIA Placement25 mils min 25 mils min 25 mils min 5.2.2Clock Signal Considerations PGA or BGA Package5.2.5USB Considerations 5.2.3SMII Signal Considerations5.2.4MII Signal Considerations 5.2.6Cross-Talk 5.2.7EMI-DesignConsiderations5.2.9Power and Ground Plane 5.2.8Trace ImpedanceFebruary Document Number 305261 RevisionFebruary Document Number 305261 Revision6.2Topology 6.0PCI Interface Design Considerations6.1Electrical Interface 6.3Clock Distribution Figure 26. PCI Address/Data TopologyPCI Slot Table 25. PCI Address/Data Routing Guidelines6.3.1Trace Length Limits PCI DevicesClock DriverFebruary 6.3.3Signal Loading6.3.2Routing Guidelines DDR Signal Groups 7.0DDR-SDRAM7.1Introduction TableFigure 28. Processor-DDRInterface ProcessorsLine of Network DDR SDRAMFebruary Document Number: 305261, Revision:Supported Memory Configurations VTT Signal Termination SignalTermination Intel IXP46X7.1.1Selecting VTT Power Supply Figure 30. VTT Terminating CircuitryIXP46X DDR SDRAMFigure 31. DDR Command and Control Setup and Hold Control/Command ValidDDR M CLK 7.1.2Signal-TimingAnalysisDDR Data to DQS Read Timing Parameters Figure 32. DDR Data to DQS Read Timing ParametersData Figure 33. DDR-Data-to-DQS-WriteTiming Parameters Data ValidDDR Data to DQS Write Timing Parameters Data7.1.3Printed Circuit Board Layer Stackup DDR-Clock-to-DQS-WriteTiming Parameters7.1.4Printed Circuit Board Controlled Impedance Figure 35. Printed Circuit Board Layer StackupFebruary 7.1.5Timing Relationships Figure 31 on page -Table 29 on page—Table 30 on page —Table 31 on page Figure 32 on page -Table 30 on page7.1.7.1Clock Group 7.1.6Resistive Compensation Register Rcomp7.1.7Routing Guidelines 7.1.7.2Data, Command, and Control Groups Clock Signal Group Routing Guidelines7.2Simulation Results 7.2.1Clock GroupFebruary Document Number: 305261, Revision:7.2.2Data Group FebruaryTL1 Tpd = 175 ps/in Figure 39. DDR Data Topology Two-Bankx16 Devices FebruaryFebruary Document Number: 305261, Revision:February February Document Number 305261, Revision7.2.3Control Group February Document Number 305261, Revision7.2.4Command Group TL1 Tpd = 175 ps/inTL2 Tpd = 175 ps/in TL3 Tpd = 175 ps/inFebruary Document Number 305261, RevisionFebruary February Document Number 305261, RevisionFebruary 7.2.5RCVENIN and RCVENOUT Figure 49. DDR RCVENIN/RCVENOUT TopologyFebruary February Document Number 305261, RevisionFebruary Document Number 305261, Revision