Overview, List of Acronyms and Abbreviations | Intel IXP45X, IXP46X

Introduction—Intel®IXP45X and Intel® IXP46X Product Line of Network Processors

1.3Acronyms and Abbreviations

	Table 1 lists the acronyms and abbreviations used in this guide.
Table 1.	List of Acronyms and Abbreviations

	Term	Explanation

	AHB	Advanced High-Performance Bus

	APB	Advanced Peripheral Bus

	ATM	Asynchronous Transfer Mode

	DDR	Double Data Rate

	EMI	Electro-Magnetic Interference

	GPIO	General Purpose Input/Output

	HSS	High Speed Serial

	I2C	Inter-Integrated Circuit

	IP	Internet Protocol

	ISA	Instruction Set Architecture

	LAN	Local Area Network

	MII	Media-Independent Interface

	NPE	Network Processor Engine

	PCB	Printed Circuit Board

	PCI	Peripheral Component Interface

	PHY	Physical Layer Interface

	PLL	Phase-Locked Loop

	PMU	Performance Monitoring Unit

	SDRAM	Synchronous Dynamic Random Access Memory

	SME	Small-to-Medium Enterprise

	SMII	Serial Media-Independent Interface

	SSP	Synchronous Serial Protocol

	UART	Universal Asynchronous Receiver-Transmitter

	USB	Universal Serial Bus

	VTT	Termination Voltage Supply

1.4Overview

The IXP45X/IXP46X network processors are highly integrated devices, capable of interfacing with most common industry standard peripherals, required for high- performance control applications.

Note: This document discusses all features supported on the Intel® IXP465 Network Processor. A subset of these features is supported by certain processors in the IXP45X/ IXP46X product line, such as the Intel® IXP460 or Intel® IXP455 network processors. For details on feature support listed by processor, see the Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Datasheet.

Some of the key features of the IXP45X/IXP46X network processors, when used as a single-chip solution for embedded applications, are as follows:

•Intel XScale® Processor (compliant with Intel® StrongARM* architecture) — Up to 667 MHz

	Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
December 2006	HDD
Document Number: 305261; Revision: 004	11

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Intel IXP45X, IXP46X manual Overview, List of Acronyms and Abbreviations, Term Explanation

Contents

February Hardware Design Guidelines HDD Contents 12.1 Figures Tables Control Group Topology Transmission Line Characteristics Date Revision Description Revision History HDD Chapter Name Description Content Overview Title Document # Related Documentation Term Explanation OverviewList of Acronyms and Abbreviations Smii Intel IXP465 Component Block Diagram Dslam Typical Applications System Memory Map System Architecture Description Intel IXP465 Example System Block Diagram Symbol Description Soft Fusible FeaturesSignal Type Definitions DDR Sdram Interface Pin Description Sheet 1 Signal InterfaceSoft Fusible Features DDR-266 Sdram Interface Ddrircomp DDR Sdram Interface Pin Description Sheet 2Ddriwen Ddrircveninn DDR Sdram Initialization Expansion BusDDR Sdram Memory Interface Input Pull Name Recommendations Output Down Reset Configuration StrapsExpansion Bus Signal Recommendations Name Function Description Boot/Reset Strapping Configuration Sheet 1 4 16-Bit Device Interface Boot/Reset Strapping Configuration Sheet 23 8-Bit Device Interface 5 32-Bit Device Interface Bit Device 16/32-Bit Device Interface Byte Enable Flash Interface Example Flash Interface Design Notes Uart InterfaceSram Interface Name Input Pull Recommendations Output Down Uart Signal Recommendations Uart Interface Example MII/SMII Interface MII NPE B Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations MII NPE C Signal Recommendations MII NPE B Signal Recommendations Sheet 2 NPE A,B,C MAC Management Signal Recommendations NPE A,B,CDevice Connection, MII Smii Signal Recommendations NPE A, B, C Signal Interface, Smii Device Connection, Smii Gpio Interface Gpio Signal Recommendations Device Connection I2C Signal RecommendationsI2C Interface I2C Eeprom Interface Example USB Interface USB Host/Device Signal Recommendations Host Device USB Device Interface Example Utopia Level 2 Interface Utopia Signal Recommendations Utopia Interface Example HSS Interface HSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0 HSSRXCLK1 HSSTXDATA1HSSTXCLK1 HSSRXDATA1 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface Input Pull Name Outpu Recommendations Down PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block Diagram PCI Interface Supporting 5 V PCI Interface PCI Host/Option Interface Pin Description Sheet 1 PCI Option Interface PCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Oscillator Clock SignalsClock Signals Input System Clock Name Nominal Description Voltage PowerPower Interface Sheet 1 VCC De-Coupling Power SequenceReset Timing De-Coupling Capacitance Recommendations HDD HDD Component Selection Component PlacementPCB Overview General Recommendations Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations USB Considerations Smii Signal ConsiderationsMII Signal Considerations EMI-Design Considerations Cross-Talk Trace Impedance Power and Ground Plane HDD @66 MHz Electrical InterfaceTopology @33 MHz Parameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading DDRIDQS40 DDR Signal GroupsGroup Signal Name Description No of Single Ended Signals Introduction DDR Sdram HDD Clock Banks Memory Size Supported Memory Configurations VTT VTT Terminating Circuitry Selecting VTT Power Supply Ddrmclk DDR Command and Control Setup and Hold ValuesSymbol Parameter Min Max Units DDR Data to DQS Read Timing Parameters DDR Data to DQS Write Timing Parameters DDR-Data-to-DQS-Write Timing Parameters Printed Circuit Board Layer Stackup Printed Circuit Board Layer Stackup Printed Circuit Board Controlled Impedance Printed Circuit Board Controlled Impedance Timing Relationships Signal Group Absolute Minimum Absolute Maximum LengthTiming Relationships Clock Group Resistive Compensation Register Rcomp DDRIBA10, DDRIRASN, DDRICASN, Ddriwen Clock Signal Group Routing GuidelinesData, Command, and Control Group Routing Guidelines Parameter Definition Transmission Line Length Clock Group Topology Transmission Line CharacteristicsSimulation Results Clock Group DDR Clock Topology Two-Bank x16 Devices DDR Clock Simulation Results Two-Bank x16 Devices Data Group Data Group Topology Transmission Line Characteristics DDR Data Topology Two-Bank x16 Devices DDR Data Write Simulation Results Two-Bank x16 Devices HDD HDD Control Group Control Group Topology Transmission Line Characteristics DDR RAS Simulation Results Two-Bank x16 Devices Command Group Topology Transmission Line Characteristics Command Group DDR Command MA3 Topology Two-Bank x16 Devices DDR Address Simulation Results Two-Bank x16 Devices DDR Command RAS Topology Two-Bank x16 Devices 104 DDR RCVENIN/RCVENOUT Topology Rcvenin and Rcvenout DDR RCVENIN/RCVENOUT Simulation Results Rseries = 0 Ω DDR RCVENIN/RCVENOUT Simulation Results Rseries = 60 Ω 108