Hardware Design Guidelines
February
Document No 305261 Revision
February
Introduction
Contents
5.0 General Layout and Routing Guide
February
6.0 PCI Interface Design Considerations
Document Number 305261, Revision
Figures
Tables
Date
Revision History
Revision
Description
February
1.0Introduction
1.1Content Overview
1.2Related Documentation
1.3Acronyms and Abbreviations
1.4Overview
List of Acronyms and Abbreviations
32-bitPCI interface Master/Target 33/66 MHz
MII/SMII
Figure 1. Intel IXP465 Component Block Diagram
Cryptography
Unit
1.5Typical Applications
2.0System Architecture
2.1System Architecture Description
2.2System Memory Map
IntelIXP46X Product
JTAG
Line of Network
Processors
Signal Type Definitions
3.1Soft Fusible Features
3.0General Hardware Design Considerations
Table
Soft Fusible Features
3.2.1Signal Interface
3.2DDR-266SDRAM Interface
DDR SDRAM Interface Pin Description Sheet 1 of
DDR SDRAM Interface Pin Description Sheet 2 of
3.3Expansion Bus
3.2.2DDR SDRAM Memory Interface
3.2.3DDR SDRAM Initialization
3.3.1Signal Interface
3.3.2Reset Configuration Straps
Expansion Bus Signal Recommendations
Table
Boot/Reset Strapping Configuration Sheet 1 of
Name
Function
Boot/Reset Strapping Configuration Sheet 2 of
3.3.38-BitDevice Interface
3.3.416-BitDevice Interface
3.3.532-BitDevice Interface
16-Bit-WordAccess
Byte Access
32-Bit-WordAccess
8-BitDevice
16-Bit-WordAccess
Byte Access
32-Bit-WordAccess
8-BitDevice
3.3.6Flash Interface
Intel Flash
Figure 5. Flash Interface Example
16-Bit-WordAccess
3.3.7SRAM Interface
3.4UART Interface
3.3.8Design Notes
Figure 6. Expansion Bus SRAM Interface
UART Signal Recommendations
3.4.1Signal Interface
MII/SMII Interface
Connector
Figure 7. UART Interface Example
UART Interface
3.5.1Signal Interface MII
MII NPE A Signal Recommendations
MII NPE B Signal Recommendations Sheet 1 of
MII NPE C Signal Recommendations
MII NPE B Signal Recommendations Sheet 2 of
3.5.2Device Connection, MII
Figure 8. MII Interface Example
10/100
3.5.3Signal Interface, SMII
3.6GPIO Interface
3.5.4Device Connection, SMII
Figure 9. SMII Interface Example
3.6.1Signal Interface
GPIO Signal Recommendations
3.6.2Design Notes
I2C Signal Recommendations
3.7.1Signal Interface
3.7I2C Interface
3.7.2Device Connection
Figure 10. I2C EEPROM Interface Example
3.8USB Interface
Product Line
Network Processor
USB Host/Device Signal Recommendations
3.8.1Signal Interface
Figure 11. USB Host Down Stream Interface Example
3.8.2Device Connection
Host
Device
Figure 12. USB Device Interface Example
3.9UTOPIA Level 2 Interface
Device
Host
3.9.1Signal Interface
UTOPIA Signal Recommendations
3.9.2Device Connection
Figure 13. UTOPIA Interface Example
3.10HSS Interface
Analog Front
ATM Layer Device
High-Speed,Serial Interface
3.10.1Signal Interface
Transmit frame
High-Speed,Serial Interface
3.11SSP Interface
3.10.2Device Connection
Figure 14. HSS Interface Example
3.11.2Device Connection
3.11.1Signal Interface
Synchronous Serial Peripheral Port Interface
SPI Flash
3.12.1Signal Interface
3.12PCI Interface
PCI Controller Sheet 1 of
PCI Controller Sheet 2 of
3.12.2PCI Interface Block Diagram
Figure 16. PCI Interface
3.12.3Supporting 5 V PCI Interface
Compact PCI Bus
cPCI J1
3.3V Logic
3.12.4PCI Option Interface
PCI Device
PCI Device
Page
3.12.5Design Notes
3.13JTAG Interface
3.14.1Clock Signals
3.13.1Signal Interface
Clock Signals
3.14Input System Clock
3.15Power
3.14.3Device Connection
Intel IXP46X
3.15.6Reset Timing
3.15.5Power Sequence
Power Interface Sheet 2 of
3.15.1De-CouplingCapacitance Recommendations
Document Number 305261 Revision
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Document Number 305261 Revision
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4.0General PCB Guide
4.4Component Placement
4.1PCB Overview
4.2General Recommendations
4.5Stack-UpSelection
Figure 19. Component Placement on a PCB
Inexpensive
Medium Frequency
Low-impedancepower distribution
Uncontrolled signal trace impedance
Higher cost More weight
Poor routing density
Figure 21. 6-LayerStackup
Figure 20. 8-LayerStackup
5.0General Layout and Routing Guide
5.1Overview
5.2General Layout Guidelines
Figure 22. Signal Changing Reference Planes
5.2.1General Component Spacing
VIAs
Figure 24. Poor Design Practice for VIA Placement
25 mils min 25 mils min 25 mils min
Flush Via min Potential Bridge min
PGA or BGA Package
5.2.2Clock Signal Considerations
5.2.3SMII Signal Considerations
5.2.4MII Signal Considerations
5.2.5USB Considerations
5.2.7EMI-DesignConsiderations
5.2.6Cross-Talk
5.2.8Trace Impedance
5.2.9Power and Ground Plane
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Document Number 305261 Revision
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6.0PCI Interface Design Considerations
6.1Electrical Interface
6.2Topology
Figure 26. PCI Address/Data Topology
6.3Clock Distribution
PCI Slot
Table 25. PCI Address/Data Routing Guidelines
PCI Devices
6.3.1Trace Length Limits
Clock
Driver
6.3.3Signal Loading
6.3.2Routing Guidelines
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7.0DDR-SDRAM
DDR Signal Groups
7.1Introduction
Table
Processors
Figure 28. Processor-DDRInterface
Line of Network
DDR SDRAM
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February
Supported Memory Configurations
Signal
VTT Signal Termination
Termination
Intel IXP46X
Figure 30. VTT Terminating Circuitry
7.1.1Selecting VTT Power Supply
IXP46X
DDR SDRAM
Control/Command Valid
Figure 31. DDR Command and Control Setup and Hold
DDR M CLK
7.1.2Signal-TimingAnalysis
Figure 32. DDR Data to DQS Read Timing Parameters
Data
DDR Data to DQS Read Timing Parameters
Data Valid
Figure 33. DDR-Data-to-DQS-WriteTiming Parameters
DDR Data to DQS Write Timing Parameters
Data
DDR-Clock-to-DQS-WriteTiming Parameters
7.1.3Printed Circuit Board Layer Stackup
Figure 35. Printed Circuit Board Layer Stackup
7.1.4Printed Circuit Board Controlled Impedance
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Figure 31 on page -Table 29 on page
7.1.5Timing Relationships
—Table 30 on page —Table 31 on page
Figure 32 on page -Table 30 on page
7.1.6Resistive Compensation Register Rcomp
7.1.7Routing Guidelines
7.1.7.1Clock Group
Clock Signal Group Routing Guidelines
7.1.7.2Data, Command, and Control Groups
7.2.1Clock Group
7.2Simulation Results
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7.2.2Data Group
TL1 Tpd = 175 ps/in
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Figure 39. DDR Data Topology Two-Bankx16 Devices
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7.2.3Control Group
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TL1 Tpd = 175 ps/in
7.2.4Command Group
TL2 Tpd = 175 ps/in
TL3 Tpd = 175 ps/in
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Figure 49. DDR RCVENIN/RCVENOUT Topology
7.2.5RCVENIN and RCVENOUT
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Document Number 305261, Revision
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Document Number 305261, Revision
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