Cypress CY7C1268V18, CY7C1270V18 manual Write Cycle Descriptions, Comments, Remains unaltered

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CY7C1266V18, CY7C1277V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1268V18, CY7C1270V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle Descriptions

 

 

 

The write cycle description table for CY7C1266V18 and CY7C1268V18 follows.[2, 8]

 

 

 

 

BWS

0/

 

BWS

1/

K

 

 

 

 

 

 

Comments

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NWS0

 

NWS1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

L–H

 

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1266V18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1268V18 both bytes (D[17:0]) are written into the device.

 

 

 

 

L

 

L

 

L-H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1266V18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1268V18 both bytes (D[17:0]) are written into the device.

 

 

 

 

L

 

H

L–H

 

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1266V18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1268V18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

 

L

 

H

 

L–H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1266V18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1268V18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

 

H

 

L

L–H

 

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1266V18 only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1268V18 only the upper byte (D[17:9]) is written into the device, D[8:0]

remains unaltered.

 

 

H

 

L

 

L–H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1266V18 only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1268V18 only the upper byte (D[17:9]) is written into the device, D[8:0]

remains unaltered.

 

 

H

 

H

L–H

 

 

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

 

L–H

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle Descriptions

 

 

 

The write cycle description table for CY7C1277V18 follows.[2, 8]

 

 

 

 

BWS

0

 

K

 

K

 

 

 

 

 

 

Comments

 

 

 

 

L

 

L-H

 

 

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

 

 

 

L

 

L-H

 

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

 

 

 

H

 

L-H

 

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

L-H

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

8.Assumes a write cycle was initiated per the Write Cycle Descriptions tables. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are met.

Document Number: 001-06347 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1266V18 Logic Block Diagram CY7C1277V18Logic Block Diagram CY7C1268V18 Logic Block Diagram CY7C1270V18CY7C1277V18 4M x Pin ConfigurationsCY7C1266V18 4M x TMS TDIQvld CY7C1268V18 2M xCY7C1270V18 1M x BWSSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Negative Input Clock InputTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Truth Table Delay Lock Loop DLLApplication Example OperationRemains unaltered Write Cycle DescriptionsComments During the data portion of a write sequenceWritten into the device. D 359 remains unaltered Write cycle description table for CY7C1270V18 follows.2Into the device Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows.9Parameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Electrical Characteristics GND ≤ VI ≤ VDDTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Waveforms Power Up Sequence in DDR-II+ SramPower Up Sequence DLL ConstraintsMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics Operating RangeAC Test Loads and Waveforms Capacitance20Thermal Resistance20 Parameter Description Test Conditions Max UnitHigh Switching CharacteristicsParameter Min Max LOWRead/Write/Deselect Sequence29 Switching WaveformsNOP Ordering Information 333 Package Diagram Ball Fbga 15 x 17 x 1.40 mmNXR ECN No Issue Date Orig. Description of ChangeDocument History VKN