Cypress CY7C1277V18 manual Power Up Sequence in DDR-II+ Sram, Power Up Waveforms, DLL Constraints

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CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18

Power Up Sequence in DDR-II+ SRAM

DDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. During

power up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock.

Power Up Sequence

■Apply power with DOFF tied HIGH (all other inputs can be HIGH or LOW)

❐Apply VDD before VDDQ

❐Apply VDDQ before VREF or at the same time as VREF

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency.

■Provide stable power and clock (K, K) for 2048 cycles to lock the DLL

Power Up Waveforms

Figure 3. Power Up Waveforms

K

K

VDD/VDDQ

DOFF

~ ~

	~ ~

Unstable Clock	> 2048 Stable Clock	Start Normal
Clock Start (Clock Starts after VDD/VDDQ is Stable)		Operation
Clock Start (Clock Starts after VDD/VDDQ is Stable)

VDD/VDDQ Stable (< + 0.1V DC per 50 ns)

Fix HIGH (tie to VDDQ)

Document Number: 001-06347 Rev. *D

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1277V18 Logic Block Diagram CY7C1266V18Logic Block Diagram CY7C1270V18 Logic Block Diagram CY7C1268V18TMS TDI Pin ConfigurationsCY7C1266V18 4M x CY7C1277V18 4M xBWS CY7C1268V18 2M xCY7C1270V18 1M x QvldNegative Input Clock Input Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. WhenTCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Operation Delay Lock Loop DLLApplication Example Truth TableDuring the data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredInto the device. D 80 and D 3518 remain unaltered Write cycle description table for CY7C1270V18 follows.2Into the device Written into the device. D 359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State DiagramGND ≤ VI ≤ VDD TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II+ SramPower Up Sequence Power Up WaveformsOperating Range Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsParameter Description Test Conditions Max Unit Capacitance20Thermal Resistance20 AC Test Loads and WaveformsLOW Switching CharacteristicsParameter Min Max HighRead/Write/Deselect Sequence29 Switching WaveformsNOP Ordering Information 333 Ball Fbga 15 x 17 x 1.40 mm Package DiagramVKN ECN No Issue Date Orig. Description of ChangeDocument History NXR