Cypress CY7C1270V18, CY7C1268V18 Pin Configurations, CY7C1266V18 4M x, CY7C1277V18 4M x, Tms Tdi

Page 4

CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

Pin Configurations

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1266V18 (4M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

NC/144M

A

A

CQ

CQ

R/W

NWS

1

K

LD

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

DQ3

NWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

D

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ4

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

NC

DQ5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ1

NC

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

DQ6

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

N

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ7

A

A

QVLD

A

A

NC

NC

NC

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

CY7C1277V18 (4M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

NC

NC/144M

A

A

CQ

CQ

R/W

K

LD

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

DQ3

BWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

D

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ4

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

NC

DQ5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ1

NC

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

DQ6

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

N

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ7

A

A

QVLD

A

A

NC

NC

DQ8

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

Document Number: 001-06347 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1266V18 Logic Block Diagram CY7C1277V18Logic Block Diagram CY7C1268V18 Logic Block Diagram CY7C1270V18Pin Configurations CY7C1266V18 4M xCY7C1277V18 4M x TMS TDICY7C1268V18 2M x CY7C1270V18 1M xQvld BWSPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Delay Lock Loop DLL Application ExampleTruth Table OperationWrite Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle description table for CY7C1270V18 follows.2 Into the deviceWritten into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows.9TAP Controller Block Diagram TAP Electrical CharacteristicsParameter Description Test Conditions Min Max Unit GND ≤ VI ≤ VDDTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance20 Thermal Resistance20AC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Parameter Min MaxHigh LOWRead/Write/Deselect Sequence29 Switching WaveformsNOP Ordering Information 333 Package Diagram Ball Fbga 15 x 17 x 1.40 mmECN No Issue Date Orig. Description of Change Document HistoryNXR VKN