Cypress CY7C1266V18, CY7C1277V18 manual CY7C1268V18 2M x, CY7C1270V18 1M x, Qvld, Bws

Page 5

CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

Pin Configurations (continued)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1268V18 (2M x 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

NC/144M

A

A

CQ

CQ

R/W

BWS

1

K

LD

B

NC

DQ9

NC

A

NC/288M

K

0

A

NC

NC

DQ8

BWS

C

NC

NC

NC

VSS

A

NC

A

VSS

NC

DQ7

NC

D

NC

NC

DQ10

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ11

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ6

F

NC

DQ12

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ5

G

NC

NC

DQ13

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ4

NC

K

NC

NC

DQ14

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ3

L

NC

DQ15

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

DQ1

NC

N

NC

NC

DQ16

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ17

A

A

QVLD

A

A

NC

NC

DQ0

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

CY7C1270V18 (1M x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/144M

A

A

NC/72M

CQ

CQ

R/W

BWS

2

K

BWS1

LD

B

NC

DQ27

DQ18

A

3

K

0

A

NC

NC

DQ8

BWS

BWS

C

NC

NC

DQ28

VSS

A

NC

A

VSS

NC

DQ17

DQ7

D

NC

DQ29

DQ19

VSS

VSS

VSS

VSS

VSS

NC

NC

DQ16

E

NC

NC

DQ20

VDDQ

VSS

VSS

VSS

VDDQ

NC

DQ15

DQ6

F

NC

DQ30

DQ21

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ5

G

NC

DQ31

DQ22

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ14

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

DQ32

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ13

DQ4

K

NC

NC

DQ23

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ12

DQ3

L

NC

DQ33

DQ24

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

M

NC

NC

DQ34

VSS

VSS

VSS

VSS

VSS

NC

DQ11

DQ1

N

NC

DQ35

DQ25

VSS

A

A

A

VSS

NC

NC

DQ10

P

NC

NC

DQ26

A

A

QVLD

A

A

NC

DQ9

DQ0

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

Document Number: 001-06347 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1277V18 Logic Block Diagram CY7C1266V18Logic Block Diagram CY7C1270V18 Logic Block Diagram CY7C1268V18CY7C1266V18 4M x Pin ConfigurationsCY7C1277V18 4M x TMS TDICY7C1270V18 1M x CY7C1268V18 2M xQvld BWSPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Application Example Delay Lock Loop DLLTruth Table OperationComments Write Cycle DescriptionsRemains unaltered During the data portion of a write sequenceInto the device Write cycle description table for CY7C1270V18 follows.2Written into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramParameter Description Test Conditions Min Max Unit GND ≤ VI ≤ VDDTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II+ SramPower Up Waveforms DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeThermal Resistance20 Capacitance20AC Test Loads and Waveforms Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsHigh LOWNOP Switching WaveformsRead/Write/Deselect Sequence29 Ordering Information 333 Ball Fbga 15 x 17 x 1.40 mm Package DiagramDocument History ECN No Issue Date Orig. Description of ChangeNXR VKN