Pin Definitions, Pin Name Pin Description

CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

Pin Definitions

Pin Name

Pin Description

DQ[x:0]

Input/Output-

Data Input/Output Signals. Inputs are sampled on the rising edge of K and

clocks during

Synchronous

valid write operations. These pins drive out the requested data during a read operation. Valid

data is driven out on the rising edge of both the K and K clocks during read operations. When

read access is deselected, Q[x:0] are automatically tri-stated.

CY7C1266V18 – DQ[7:0]

CY7C1277V18 – DQ[8:0]

CY7C1268V18 – DQ[17:0]

CY7C1270V18 – DQ[35:0]

Input-

Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when

Synchronous

a bus cycle sequence is to be defined. This definition includes address and read/write direction.

All transactions operate on a burst of 2 data. LD must meet the setup and hold times around

edge of K.

Input-

Nibble Write Select 0, 1, Active LOW (CY7C1266V18 only). Sampled on the rising edge of

NWS

Synchronous

the K and K clocks during write operations. Used to select which nibble is written into the device

during the current portion of the write operations. Nibbles not written remain unaltered.

NWS

0 controls D[3:0] and

NWS

1 controls D[7:4].

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble

Write Select ignores the corresponding nibble of data and not written into the device.

Input-

Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and

clocks

BWS

BWS2, BWS3

Synchronous

during write operations. Used to select which byte is written into the device during the current

portion of the write operations. Bytes not written remain unaltered.

CY7C1277V18 − BWS0

controls D[8:0]

CY7C1268V18 − BWS0

controls D[8:0] and

BWS

1 controls D

[17:9].

CY7C1270V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3

controls D[35:27].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write

Select ignores the corresponding byte of data and not written into the device.

Input-

Address Inputs. Sampled on the rising edge of the K clock during active read and write opera-

Synchronous

tions. These address inputs are multiplexed for both read and write operations. Internally, the

device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1266V18, 4M x 9 (2 arrays

each of 2M x 9) for CY7C1277V18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1268V18, and

1M x 36 (2 arrays each of 512K x 36) for CY7C1270V18.

Input-

Synchronous Read/Write Input. When

is LOW, this input designates the access type (Read

R/W

Synchronous

when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the setup and

hold times around edge of K.

QVLD

Valid Output

Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ

Indicator

and CQ.

Input-

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the

Clock

device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated

on the rising edge of K.

Input-

Negative Input Clock Input.

is used to capture synchronous data being presented to the

Clock

device and to drive out data through Q[x:0] when in single clock mode.

Clock Output

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the

input clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Character-

istics” on page 22.

Clock Output

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the

input clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Character-

istics” on page 22.

Document Number: 001-06347 Rev. *D

Page 6 of 27

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