Cypress CY7C1277V18, CY7C1270V18 manual Switching Waveforms, Read/Write/Deselect Sequence29, Nop

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CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

Switching Waveforms

Read/Write/Deselect Sequence[29, 30]

Figure 5. Waveform for 2.5 Cycle Read Latency

K

NOP

1

tKH

 

READ

READ

NOP

NOP

NOP

WRITE

WRITE

READ

NOP

NOP

 

 

2

3

4

5

6

7

8

9

10

11

12

tKL

tCYC

tKHKH

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

LD

 

 

 

 

 

 

 

tSC

tHC

 

 

 

 

R/W

 

 

 

 

 

 

A

A0

A1

A2

A3

A4

 

 

 

tQVLD

 

 

 

tSA

tHA

tQVLD

 

tQVLD

 

 

 

QVLD

 

 

 

tHD

 

tHD

 

 

 

 

 

tSD

 

 

 

Q01 Q10

tSD

 

 

DQ

Q00

Q11

D20 D21

D30 D31

Q40

 

tDOH

 

 

 

 

 

tCLZ

tCHZ

 

 

 

 

tCO

 

 

tCQD

 

 

 

 

(Read Latency = 2.5 Cycles)

 

 

tCQDOH

 

 

 

 

tCCQO

 

 

 

 

 

 

tCQOH

 

 

 

 

 

 

CQ

 

t

 

 

tCQH

tCQHCQH

 

 

 

CCQO

 

 

tCQOH

 

 

 

 

 

 

 

 

 

CQ

 

 

 

 

 

 

 

 

 

 

 

 

 

DON’T CARE

UNDEFINED

Notes

29.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

30.Outputs are disabled (High-Z) one clock cycle after a NOP.

Document Number: 001-06347 Rev. *D

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1277V18 Logic Block Diagram CY7C1266V18Logic Block Diagram CY7C1270V18 Logic Block Diagram CY7C1268V18TMS TDI Pin ConfigurationsCY7C1266V18 4M x CY7C1277V18 4M xBWS CY7C1268V18 2M xCY7C1270V18 1M x QvldNegative Input Clock Input Pin DefinitionsPin Name Pin Description Synchronous Read/Write Input. WhenTCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Operation Delay Lock Loop DLLApplication Example Truth TableDuring the data portion of a write sequence Write Cycle DescriptionsComments Remains unalteredInto the device. D 80 and D 3518 remain unaltered Write cycle description table for CY7C1270V18 follows.2Into the device Written into the device. D 359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State DiagramGND ≤ VI ≤ VDD TAP Controller Block DiagramTAP Electrical Characteristics Parameter Description Test Conditions Min Max UnitTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II+ SramPower Up Sequence Power Up WaveformsOperating Range Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsParameter Description Test Conditions Max Unit Capacitance20Thermal Resistance20 AC Test Loads and WaveformsLOW Switching CharacteristicsParameter Min Max HighNOP Switching WaveformsRead/Write/Deselect Sequence29 Ordering Information 333 Ball Fbga 15 x 17 x 1.40 mm Package DiagramVKN ECN No Issue Date Orig. Description of ChangeDocument History NXR
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