Cypress CY7C1266V18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

Identification Register Definitions

	Instruction		Value			Description
	Field	CY7C1266V18	CY7C1277V18	CY7C1268V18	CY7C1270V18	Description
	Field

	Revision	000	000	000	000	Version number.
	Number (31:29)
	Cypress Device	11010111000000111	11010111000001111	11010111000010111	11010111000100111	Defines the type
	ID (28:12)					of SRAM.
	Cypress JEDEC	00000110100	00000110100	00000110100	00000110100	Enables unique
	ID (11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an
						ID register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	109

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input/output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between
		TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input/output contents. Places the boundary scan register between
		TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input/output ring contents. Places the boundary scan register
		between TDI and TDO. Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect
		SRAM operation.

Document Number: 001-06347 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1277V18 Logic Block Diagram CY7C1266V18Logic Block Diagram CY7C1270V18 Logic Block Diagram CY7C1268V18CY7C1266V18 4M x Pin ConfigurationsCY7C1277V18 4M x TMS TDICY7C1270V18 1M x CY7C1268V18 2M xQvld BWSPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Application Example Delay Lock Loop DLLTruth Table OperationComments Write Cycle DescriptionsRemains unaltered During the data portion of a write sequenceInto the device Write cycle description table for CY7C1270V18 follows.2Written into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows.9 TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramParameter Description Test Conditions Min Max Unit GND ≤ VI ≤ VDDTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II+ SramPower Up Waveforms DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeThermal Resistance20 Capacitance20AC Test Loads and Waveforms Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsHigh LOWNOP Switching WaveformsRead/Write/Deselect Sequence29 Ordering Information 333 Ball Fbga 15 x 17 x 1.40 mm Package DiagramDocument History ECN No Issue Date Orig. Description of ChangeNXR VKN