Cypress CY7C1270V18, CY7C1266V18, CY7C1268V18, CY7C1277V18 manual Ordering Information

Page 24

CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
400	CY7C1266V18-400BZC	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1277V18-400BZC

	CY7C1268V18-400BZC

	CY7C1270V18-400BZC

	CY7C1266V18-400BZXC	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1277V18-400BZXC

	CY7C1268V18-400BZXC

	CY7C1270V18-400BZXC

	CY7C1266V18-400BZI	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1277V18-400BZI

	CY7C1268V18-400BZI

	CY7C1270V18-400BZI

	CY7C1266V18-400BZXI	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1277V18-400BZXI

	CY7C1268V18-400BZXI

	CY7C1270V18-400BZXI

375	CY7C1266V18-375BZC	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1277V18-375BZC

	CY7C1268V18-375BZC

	CY7C1270V18-375BZC

	CY7C1266V18-375BZXC	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1277V18-375BZXC

	CY7C1268V18-375BZXC

	CY7C1270V18-375BZXC

	CY7C1266V18-375BZI	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1277V18-375BZI

	CY7C1268V18-375BZI

	CY7C1270V18-375BZI

	CY7C1266V18-375BZXI	51-85195	165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1277V18-375BZXI

	CY7C1268V18-375BZXI

	CY7C1270V18-375BZXI

Document Number: 001-06347 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1266V18 Logic Block Diagram CY7C1277V18Logic Block Diagram CY7C1268V18 Logic Block Diagram CY7C1270V18Pin Configurations CY7C1266V18 4M xCY7C1277V18 4M x TMS TDICY7C1268V18 2M x CY7C1270V18 1M xQvld BWSPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Negative Input Clock InputPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Delay Lock Loop DLL Application ExampleTruth Table OperationWrite Cycle Descriptions CommentsRemains unaltered During the data portion of a write sequenceWrite cycle description table for CY7C1270V18 follows.2 Into the deviceWritten into the device. D 359 remains unaltered Into the device. D 80 and D 3518 remain unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller follows.9TAP Controller Block Diagram TAP Electrical CharacteristicsParameter Description Test Conditions Min Max Unit GND ≤ VI ≤ VDDTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II+ Sram Power Up SequencePower Up Waveforms DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance20 Thermal Resistance20AC Test Loads and Waveforms Parameter Description Test Conditions Max UnitSwitching Characteristics Parameter Min MaxHigh LOWSwitching Waveforms Read/Write/Deselect Sequence29NOP Ordering Information 333 Package Diagram Ball Fbga 15 x 17 x 1.40 mmECN No Issue Date Orig. Description of Change Document HistoryNXR VKN